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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages.
Freescale Semiconductor Advance Information
Document Number: MC13892 Rev. 2.0, 10/2009
Power Management and User Interface IC
The 13892 is a Power Management and User Interface components for Freescale's i.MX51, i.MX37, i.MX35 and i.MX27 application processors, targeting personal media players and personal navigation devices.
Features * Battery charger system for wall charging and USB charging * 10 bit ADC for monitoring battery and other inputs, plus a coulomb counter support module * 4 adjustable output buck converters for direct supply of the processor core and memory * 12 adjustable output LDOs with internal and external pass devices * 2 boost converters for supplying LCD backlight and RGB LEDs * Serial backlight drivers for displays and keypad, plus RGB LED drivers * Power control logic with processor interface and event detection * Real time clock and crystal oscillator circuitry, with coin cell backup and support for external secure real time clock on a companion system processor IC * Touch screen interface * SPI/I2C bus interface for control and register access. * Two package offering in 7 x 7mm and 12 x 12mm.
13892
Sample Parts Not Yet Available POWER MANAGEMENT IC
VK SUFFIX 98ASA10820D 139-PIN 7X7 BGA
VL SUFFIX 98ASA10849D 186-PIN 12X12 BGA
ORDERING INFORMATION
Device PC13892VK/R2* PC13892VL/R2* PC13892JVK/R2 PC13892JVL/R2 * ITC effected products -30C to 85C Temperature Range (TA) Package 7x7 12x12 7x7 12x12
BT (+FM)
DRAM
IRDA TV Out
Camera
MMC
Line In/Out Stereo Loudspeakers
SSI
Audio
Mic Inputs
IC Aud AP
USB
i.MX51 Apps Processor
Display Backlight
Stereo headphones Power
NVR
Camera
SPI/I2C
Power UI Backlight
UI
Adapter
Charger LED Li Ion Battery
MC13892 Power Mgmt & User Interface AP
Aud& Pwr Mgmt
RGB Color Indicators Touch Screen
Coin Cell Battery
Light Sensor Thermistor
CALENDAR
RTC
Figure 1. 13892 Typical Operating Circuit
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2009. All rights reserved.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations
Parameter Package size Pitch Pinout Junction to Ambient Natural Convection Junction to Ambient Natural Convection Junction to Ambient (@ 200 ft/min) Junction to Ambient (@ 200 ft/min) Junction to Board Junction to Case Junction to Package Top Natural Convection Single layer board (1s) Single layer board (1s) Single layer board (1s) Single layer board (1s) 104 54 88 49 32 29 7.0 Condition Value for 13982VK 7x7 0.5 Value for 13982VL 12x12 0.8 See Pin Connections 65 42 55 38 28 22 5.0 C/W C/W C/W C/W C/W C/W C/W Unit mm mm
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Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
Figure 2. 13892 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
3
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. PIN CONNECTIONS
PIN CONNECTIONS
Figure 3. 13892VK Pin Connections
13892
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Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. PIN CONNECTIONS
Figure 4. 13892VL Pin Connections Table 2. 13892 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 39.
Pin Number Pin Number on the on the 13982VK 13982VL A1, A2, B1 A3 A4 A2 A3 A5 Pin Name VUSB2 VINUSB2 SWBSTIN Pin Function Output Power Power Formal Name USB 2 Supply USB 2 Supply Input Switcher Boost Power Input Definition Output regulator for USB PHY Input regulator VUSB2 Switcher BST input
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Analog Integrated Circuit Device Data Freescale Semiconductor
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. PIN CONNECTIONS
Table 2. 13892 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 39.
Pin Number Pin Number on the on the 13982VK 13982VL A5 A6 A7 A8 A9 A10 D5 D8 A7 A8 A9 A10 Pin Name GNDSWBST GNDSWLED SWLEDOUT MODE VCORE BATT Pin Function Ground Ground Output Input Output Input Formal Name Switcher Boost Ground Switcher LED Ground Switcher LED Output Mode Configuration Core Supply Battery Connection Definition Ground for switcher BST Ground for boost converter for serial LED drive Boost converter output for serial LED drive USB LBP mode, normal mode, test mode selection & anti-fuse bias Regulated supply output for the IC analog core circuitry 1. Battery positive terminal 2. Battery current sensing point 2 3. Battery supply voltage sense A11 A11 CHRGRAW I/O Charger Input 1. Charger input 2. Output to battery supplied accesories A12, A13, B13 B2 B3 B4 B5 B6 B7 B8 B9 B10 A12 B2 C2 A4 C4 C6 B5 B9 C9 B11 CHRGCTRL2 GPO1 DVS2 SWBSTOUT LEDB LEDKP LEDR GNDCORE VCOREDIG BP Output Output Input Power Output Output Output Ground Output Power Charger Control 2 General Purpose Output 1 Dynamic Voltage Scaling Control 2 Driver output for charger path FETs M2 General purpose output 1 Switcher 2 DVS input pin
Switcher Boost Output Switcher BST BP supply LED Driver LED Driver LED Driver Core Ground Digital Core Supply Battery Plus General purpose LED driver output Blue Keypad lighting LED driver output General purpose LED driver output Red Ground for the IC core circuitry Regulated supply output for the IC digital core circuitry 1. Application supply point 2. Input supply to the IC core circuitry 3. Application supply voltage sense
B11 B12 C1 C2 C12 C13 D1 D2 D4 D5 13892
D9 B13 E3 B1 A13 B14 D1 C1 C3 D7
CHRGCTRL1 BATTISNSCC VINPLL VSDDRV CHRGISNS BATTISNS VUSB VSD SWBSTFB LEDMD
Output Input Power Output Input Input Output Output Input Output
Charger Control 1 Battery Current Sense PLL Supply Input VSD Driver Charger Current Sense Battery Current Sense USB Supply SD Card Supply Switcher Boost Feedback LED Driver
Driver output for charger path FETs M1 Accumulated current counter current sensing point Input regulator processor PLL Drive output regulated SD card Charge current sensing point 1 Battery current sensing point 1 USB transceiver regulator output Output regulator SD card Switcher BST feedback Main display backlight LED driver output
6
Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. PIN CONNECTIONS
Table 2. 13892 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 39.
Pin Number Pin Number on the on the 13982VK 13982VL D6 D7 D8 D9 B7 B8 B10 C10 Pin Name DVS1 REFCORE CHRGSE1B LICELL Pin Function Input Output Input I/O Formal Name Dynamic Voltage Scaling Control 1 Core Reference Charger Select Coin Cell Connection Definition Switcher 1DVS input pin Main bandgap reference Charger forced SE1 detection input 1. Coin cell supply input 2. Coin cell charger output D10 D12 C11 C12 BATTFET BPSNS Output Input Battery FET Connection Battery Plus Sense Driver output for battery path FET M3 1. BP sense point 2. Charge current sensing point 2 D13 E1 D11 E1 PWRON1 UVBUS Input I/O Power On 1 USB Bus Power on/off button connection 1 1. USB transceiver cable interface 2. VBUS & OTG supply output E2 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 F1 F2 F4 F5 F6 D2 C5 D6 B6 C8 B12 D10 E11 D13 E13 G13, G14 G1, G2 F2 G3 C7 A6, B3, B4, D3, D4, E4, E5, E6 E7, E8, E9, E10, F4, F5, F6 F7, F8, F9, F10, G4, G5, G6, G7, G8 C13 VPLL LEDG GNDLED UID PUMS2 GNDCHRG CHRGLED PWRON2 ADTRIG INT GNDSW1 GNDSW3 VBUSEN SW3FB LEDAD GNDSUB1 Output Output Ground Input Input Ground Output Input Input Output Ground Ground Input Input Output Ground Voltage Supply for PLL PWM Driver for Green LED LED Ground USB ID Power Up Mode Select 2 Charger Ground Charger LED Power On 2 ADC Trigger Interrupt Signal Switcher 1 Ground Switcher 3 Ground VBUS Enable Switcher 3 Feedback Auxiliary Display LED Ground 1 Output regulator processor PLL General purpose LED driver output Green Ground for LED drivers USB OTG transceiver cable ID Power up mode supply setting 2 Ground for charger interface Trickle LED driver output 1 Power on/off button connection 2 ADC trigger input Interrupt to processor Ground for switcher 1 Ground for switcher 3 External VBUS enable pin for OTG supply Switcher 3 feedback Auxiliary display backlight LED driver output Non critical signal ground and thermal heat sink
F7
GNDSUB2
Ground
Ground 2
Non critical signal ground and thermal heat sink
F8
GNDSUB3
Ground
Ground 3
Non critical signal ground and thermal heat sink
F9
GPO3
Output
General Purpose Output 3
General purpose output 3
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Analog Integrated Circuit Device Data Freescale Semiconductor
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. PIN CONNECTIONS
Table 2. 13892 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 39.
Pin Number Pin Number on the on the 13982VK 13982VL F10 F11 F12 F13 G1 G2 G4 G5 G6 E12 E14 F13 F14 F1 F3 J3 E2 G9, G10, G11, H3, H5, H6, H7, H8 H9, H10, H12, J5, J6, J7 J8, J9, J10, K4, K5, K6, K7 C14 F12 D14 H13, H14 H1, H2 P2 L3 N4 K8, K10, L4, L5, L6, L10 P5, P7, P8, P9, P10 Pin Name GPO2 RESETBMCU RESETB SW1OUT SW3OUT VINUSB SW4FB GNDREG2 GNDSUB4 Pin Function Output Output Output Output Output Input Input Ground Ground Formal Name General Purpose Output 2 MCU Reset Peripheral Reset Switcher 1 Output Switcher 3 Output VUSB Supply Input Switcher 4 Feedback Regulator 2 Ground Ground 4 Definition General purpose output 2 Reset output for processor Reset output for peripherals Switcher 1 output Switcher 3 output Input option for UVUSB; tie to SWBST at top level Switcher 4 feedback Ground for regulators 2 Non critical signal ground and thermal heat sink
G7
GNDSUB5
Ground
Ground 5
Non critical signal ground and thermal heat sink
G8
GNDSUB6
Ground
Ground 6
Non critical signal ground and thermal heat sink
G9 G10 G12 G13 H1 H2 H4 H5 H6 H7 H8 H9 H10 H12 H13 J1 J2
PUMS1 WDI GPO4 SW1IN SW3IN MISO GNDSPI GNDREG3 GNDSUB7 GNDSUB8 GNDSUB9
Input Input Output Input Power I/O Ground Ground Ground Ground Ground Ground Input Input Input Power Input
Power Up Mode Select 1 Watchdog Input General Purpose Output 4 Switcher 1 Input Switcher 3 Input Master In Slave Out SPI Ground Regulator 3 Ground Ground 7 Ground 8 Ground 9 Logic Control Ground Switcher 1 Feedback Secondary Standby Signal Switcher 2 Input Switcher 4 Input Master Out Slave In
Power up mode supply setting 1 Watchdog input General purpose output 4 Input voltage for switcher 1 Switcher 3 input Primary SPI read output Ground for SPI interface Ground for regulators 3 Non critical signal ground and thermal heat sink Non critical signal ground and thermal heat sink Non critical signal ground and thermal heat sink Ground for control logic Switcher 1 feedback Standby input signal from peripherals Input voltage for Switcher 2 Switcher 4 input Primary SPI write input
F11 G12 L12 J13, J14 J1, J2 N2
GNDCTRL SW1FB STANDBYSEC SW2IN SW4IN MOSI
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Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. PIN CONNECTIONS
Table 2. 13892 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 39.
Pin Number Pin Number on the on the 13982VK 13982VL J4 J5 J6 J7 J8 J9 J10 J12 J13 K1 K2 K4 K5 K6 K7 K8 K9 K10 K12 K13 L1 L2 L12 L13 M1, N1, N2 M2 M3 M4 M5 M6 M3 M6 N11 P12 D12 M12 J12 M13 L14 L1 K3 P3 M4 L7 M8 M9 N12 P13 K12 K13, K14 K1, K2 L2 L11 L13 N1 M1 N3 M5 P6 M7 Pin Name CLK32KMCU STANDBY GNDADC GNDREG1 PWRON3 TSX1 SW2FB TSX2 SW2OUT SW4OUT SPIVCC PWGTDRV1 CLK32K VCAM CFP CFM ADIN5 ADIN6 VVIDEODRV GNDSW2 GNDSW4 CS TSY2 VVIDEO VGEN3 CLK VGEN2 VSRTC GNDRTC VINCAMDRV Pin Function Output Input Ground Ground Input Input Input Input Output Output Input Output Output Output Passive Passive Input Input Output Ground Ground Input Input Output Output Input Output Output Ground I/O Formal Name 32 kHz Clock for MCU Standby Signal ADC Ground Regulator 1 Ground Power On 3 Touch Screen Interface X1 Switcher 2 Feedback Touch Screen Interface X2 Switcher 2 Output Switcher 4 Output Definition 32 kHz clock output for processor Standby input signal from processor Ground for A to D circuitry Ground for regulators 1 Power on/off button connection 3 Touch screen interface X1 Switcher 2 feedback Touch screen interface X2 Switcher 2 output Switcher 4 output
Supply Voltage for SPI Supply for SPI bus and audio bus Power Gate Driver 1 32 kHz Clock Camera Supply Current Filter Positive Power gate driver 1 32 kHz clock output for peripherals Output regulator camera Accumulated current filter cap plus terminal
Current Filter Negative Accumulated current filter cap minus terminal ADC Channel 5 Input ADC Channel 6 Input VVIDEO Driver Switcher 2 Ground Switcher 4 Ground Chip Select Touch Screen Interface Y2 Video Supply General Purpose Regulator 3 Clock General Purpose Regulator 2 SRTC Supply Real Time Clock Ground Camera Regulator Supply Input and Driver Output ADC generic input channel 5 ADC generic input channel 6 Drive output regulator VVIDEO Ground for switcher 2 Ground for switcher 4 Primary SPI select input Touch screen interface Y2 Output regulator TV DAC Output GEN3 regulator Primary SPI clock input Output GEN2 regulator Output regulator for SRTC module on processor Ground for the RTC block 1. Input regulator camera using internal PMOS FET. 2. Drive output regulator for camera voltage using external PNP device.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. PIN CONNECTIONS
Table 2. 13892 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 39.
Pin Number Pin Number on the on the 13982VK 13982VL M7 M8 M9 M10 M11 M12 M13, N12, N13 N3 N8 L9 P11 M10 N13 M14 N14 M2 Pin Name PWGTDRV2 VDIG VINDIG VGEN1DRV ADIN7 TSY1 TSREF VINGEN3DRV Input Input Output Power/ Output Output Input Input Power Output Output Input Output Pin Function Output Output Input Formal Name Power Gate Driver 2 Digital Supply VDIG Supply Input 5.5 ADC Channel 7 Input Touch Screen Interface Y1 Touch Screen Reference VGEN3 Supply Input and Driver Output VGEN2 Driver Crystal Connection 2 Crystal Connection 1 Audio Supply Input Audio Supply High Voltage IO Supply High Voltage IO Supply Input General Purpose Regulator 1 Definition Power gate driver 2 Output regulator digital Input regulator digital Drive output gen1 regulator ADC generic input channel 7, group 1 Touch screen interface Y1 Touch screen reference 1. Input VGEN3 regulator 2. Drive VGEN3 output regulator Drive output GEN2 regulator 32.768 kHz oscillator crystal connection 2 32.768 kHz oscillator crystal connection 1 Input regulator VAUDIO Output regulator for audio Output regulator high voltage IO, efuse Input regulator high voltage IO Input GEN1 regulator
N4 N5 N6 N7 N8 N9 N10 N11
P4 N5 N6 L8 N7 N9 N10 M11
VGEN2DRV XTAL2 XTAL1 VINAUDIO VAUDIO VIOHI VINIOHI VGEN1
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Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Charger and USB Input Voltage(1) Serial LED Circuitry Voltages MODE pin Voltage Battery Voltage Coin Cell Voltage ESD Voltage(2) VCHRGR VSWLED VMODE VBATT VLICELL VESD 1500 -0.3 to 20 -0.3 to 28 -0.3 to 9.0 -0.3 to 4.8 -0.3 to 3.6 V V V V V V Symbol Value Unit
Human Body Model - HBM with Mode pin excluded THERMAL RATINGS Ambient Operating Temperature Range Operating Junction Temperature Range Storage Temperature Range THERMAL RESISTANCE Peak Package Reflow Temperature During Reflow(3), (4) TPPRT TA TJ TSTG
-30 to +85 -30 to +125 -65 to +150
C C C
Note 4
C
Notes 1. USB Input Voltage applies to UVBUS pin only 2. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 3. 4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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Analog Integrated Circuit Device Data Freescale Semiconductor
11
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics Characteristics noted under conditions - 30C TA 85C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Currents valid over entire operating temperature range, except at 25C only. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included.
Characteristic CURRENT CONSUMPTION RTC Mode All blocks disabled, no main battery attached, coin cell is attached to LICELL VSRTC CLK32KMCU (20 pF load) RTC RTC Calibration module (optional) OFF Mode (All blocks disabled, main battery attached) 13892 core and RTC module Power Cut Mode (All blocks disabled, no main battery attached, coin cell is attached and valid) 13892 core and RTC module ON Standby mode - Low power mode 13892 core and RTC module Trimmed references 4 buck switches in low power mode 3 regulators(5) Total ON Mode - Typical use case 13892 core and RTC module Trimmed references 4 buck switches in PWMPS mode 5 Regulators(6) Total Notes 5. VPLL, VIOHI, VGEN2 6. VPLL, VIOHI, VGEN2, VAUDIO, VVIDEO ICOREON ITREFON ISWON IREGON ION 10 20 345 84 459 20 30 610 121.5 1000 ICORESTBY ITREFSTBY ISWSTBY IREGSTBY ISTBY 10 20 60 24 114 20 30 120 31.5 200 A IPCUT 3.0 6.0 A ISRTC ICLK32KMCU IRTC IRTCMOD IOFF 10 20 A 0.80 1.00 2.00 1.00 1.00 1.10 5.00 2.00 A A Symbol Min Typ Max Unit
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Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (Continued) Currents valid over entire operating temperature range, except at 25C only. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included.
Characteristic 32X CRYSTAL OSCILLATOR Operating Voltage Oscillator and RTC Block from BP Coincell Disconnect Threshold At LICELL Operating Current XTAL Oscillator and RTC Module RTC Mode: All blocks disabled, no main battery attached, coin cell is attached to LICELL Calibration system Output Low CLK32K, CLK32KMCU Output sink 100 A Output High CLK32K Output source 100 A CLK32KMCU Output source 100 A VSRTC GENERAL Operating Input Voltage Range VINMIN to VINMAX Valid Coin Cell range Or valid BP Operating Current Load Range ILMIN to ILMAX Bypass Capacitor Value VSRTC ACTIVE MODE - DC Output Voltage VOUT VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 CLK AND MISO Input Low CS, MOSI, CLK VINCSLO VINMOSILO VINCLKLO VINCSHI VINMOSIHI VINCLKHI VOMISOLO VOINTLO 0 0.3*SPIVC
C
Symbol
Min
Typ
Max
Unit
VXTAL 1.2 VLCD 1.8 IXTALRTC IXTALC VCLKLO 0 VCLKHI VCLKMCUHI 0.2 2.0 4.65
V
V
A 2.0 1.0 5.0 2.0 V
V SPIVCC0.2 VSRTC-0.2 SPIVCC VSRTC
V VLICELL BP ISRTC CSRTC 1.8 UVDET 0 1.0 3.6 4.65 50 A F
VSRTC 1.15 IRTCQS 0.8 1.0 1.20 1.25
V
A
V
Input High CS, MOSI, CLK
V 0.7*SPIVC
C
-
SPIVCC+0. 3 V
Output Low MISO, INT Output sink 100 A Output High MISO, INT Output source 100 A SPIVCC Operating Range
0
-
0.2 V
VOMISOHI VOINTHI SPIVCC
SPIVCC0.2 1.75
-
SPIVCC 3.1 V
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Analog Integrated Circuit Device Data Freescale Semiconductor
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (Continued) Currents valid over entire operating temperature range, except at 25C only. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included.
Characteristic BUCK CONVERTERS Operating Input Voltage PWM operation, 0 < IL < IMAX PFM operation, 0 < IL < IMAX Extended PWM or PFM operation(7) Output Voltage Range Switcher 1 Switchers 2, 3, and 4 Output Accuracy PWM mode including ripple, load regulation, and transients (8) PFM Mode, including ripple, load regulation, and transients SW1-SW2 Output Delta Voltage SW1 and SW2 both programmed for 1.250 V, PWM mode, IL = 0.5*ILMAX Maximum Continuous Load Current, IMAX, VINMIN(10)
Symbol
Min
Typ
Max
Unit
VSWIN 3.0 2.8 UVDET VSW1 0.6 0.6 VSWLOPP VSWLIPPI VSW ISW1 900 1050 ISW2 ISW3 ISW4 ISW1, 2, 3, 4 ISWPK 920 850 1700 1700 25 800 800 800 50 25 1.375 1.850 4.65 4.65 4.65
V
V
mV Nom-50 Nom-50 Nom Nom Nom+50 Nom+50 mV
mA
mA
mV A
PWM Mode, IL=0 mA; device not switching PFM Mode, IL=0 mA; device not switching Automatic Mode Change Threshold, Switchover between PFM and PWM modes
In the extended operating range the performance may be degraded Transient loading for load steps of ILmax/2 No current limiter interaction for SW1 up to 920 mA and for SW2-4 up to 850 mA . In this mode, current limit protection is disabled. Therefore, the load on SW1 should not exceed 1.05 A Guaranteed by design.
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Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (Continued) Currents valid over entire operating temperature range, except at 25C only. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included.
Characteristic BUCK CONVERTERS (CONTINUED) External Components, Used as a condition for all other parameters Inductor for SW2, SW3, SW4(11) Inductor for SW1
(11)
Symbol
Min
Typ
Max
Unit
LSW234 LSW1 RWSW COSW234 COSW1 ESRSW
-20% -20% -35% -35% 5.0 1.0
2.2 1.5 10 2x22 4.7
+20% +20% 0.16 +35% +35% 50 -
H H F F m F
Inductor Resistance Bypass Capacitor for SW2, SW3, SW4(13) Bypass Capacitor for SW1 Bypass Capacitor ESR Input Capacitor(15) SWBST Average Output Voltage(16) 3.0 V < VIN < 4.65 (1), 0 < IL < ILMAX Output Ripple(11) 3.0 V < VIN < 4.65, 0 < IL < ILMAX, Excluding reverse recovery of Schottky diode Average Load Regulation VIN = 3.6 V, 0 < IL < ILMAX Average Line Regulation 3.0 V < VIN < 4.65 V, IL = ILMAX
(17) (14)
VBST Nom-5% VBSTPP VBSTLOR VBSTLIR 50 0.5 120 5.0 Nom+5%
V
mVpp
mV/mA
mV
Notes 12. Preferred device TDK VLS252012 series at 2.5x2.0 mm footprint and 1.2 mm max height 13. Preferably 0603 style 6.3 V rated X5R/X7R type at 35% total make tolerance, temperature spread and DC bias derating such as TDK C1608X5R0J106M 14. Preferably 0805 style 6.3 V rated X5R/X7R type at 35% total make tolerance, temperature spread and DC bias derating such as TDK C2012X5R0J226M 15. Preferably 0603 style 6.3 V rated X5R/X7R type at 35% total make tolerance, temperature spread and DC bias derating such as TDK C1608X5R0J475 16. Output voltage when configured to supply VBUS in OTG mode can be as high as 5.75 V 17. Vin is the low side of the inductor that is connected to BP.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (Continued) Currents valid over entire operating temperature range, except at 25C only. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included.
Characteristic SWBST (CONTINUED) Maximum Continuous Load Current ILMAX 3.0 V < VIN < 4.65, VOUT = 5.0 V Peak Current Limit(11) At SWBSTIN; VIN = 3.6 V Start-up Overshoot IL = 0 mA Efficiency, IL = ILMAX Bias Current Consumption(11) SWBSTEFF IBSTBIAS LBST R_WBST ILSAT COBST ESRBST CBSTD IBSTDPK IBSTDPK
(11)
Symbol
Min
Typ
Max
Unit
IBST 300 BSTPK 700 VBSTOS 65 80 390 500 1200 1500 -
mA
mA
mV
% A
External Components - Used as a condition for all other parameters Inductor(18) Inductor Resistance Inductor saturation current at 30% loss in inductance value Bypass Capacitor Input Capacitor Diode current capability Diode current capability NMOS Off Leakage, SWBSTIN = 4.5 V, SWBSTEN = 0 SWLEDOUT Output Voltage Range at VSWLED(11) Current Load capability(11) VSWLED = 25.5 V LED Driver Headroom 8.0 V< VSWLED < 25.5 V External Components Inductor Capacitor(20) LLED COLED 3.3 4.7 (30 V) Or 2x10 (16 V) in series Input Capacitor 2.2 4.7 H F VLEDHR VSWLED ILED 30 0.3 60 0.6 V BP 25.5 V mA
(19)
-20% 1.0 -60% 1.0 1.0 850 1500 -
2.2 10 4.7 1.0
+20% 0.2 +35% 10 5.0
H A F m F mAdc mApk A
Bypass Capacitor ESR at resonance
IBSTIK
-
Notes 18. Preferred device TDK VLS252012 series at 2.5x2.0 mm footprint and 1.2 mm max height 19. Applications of SWBST should take into account impact of tolerance and voltage derating on the bypass capacitor at the output level. 20. The typical value represents the nominal rated value of the capacitor and takes into account the strong derating as a function of DC voltage.
13892
16
Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (Continued) Currents valid over entire operating temperature range, except at 25C only. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included.
Characteristic VVIDEO Operating Input Voltage Range VINMIN to VINMAX Operating Current Load Range ILMIN to ILMAX (Not exceeding PNP max power) Extended input voltage range (performance may be out of specification) Minimum Bypass Capacitor Value Used as a condition for all other parameters Bypass Capacitor ESR 10 kHz -1.0 MHz VVIDEO ACTIVE MODE DC Output Voltage VOUT Vinmin < VIN < VINMAX, ILMIN < IL < ILMAX Load Regulation 1.0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX Line Regulation VINMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 VVIDEO LOW POWER MODE DC - VVIDEOMODE=1 Output Voltage VOUT VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP Current Load Range ILminlp to ILMAXLP Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 VAUDIO Operating Input Voltage Range VINMIN to VINMAX Operating Current Load Range ILMIN to ILMAX Extended input voltage range (performance may be out of specification) Minimum Bypass Capacitor Value Bypass Capacitor ESR 10 kHz -1.0 MHz COAUDIO ESRAUDIO 0 0.1 VAUDIO IAUDIO VNOM+0.2 5 0 UVDET 0.65 2.2 4.65 150 4.65 V mA V F IVIDEOLO IVIDEOQSLO 8.0 10.5 VVIDEOLO VNOM - 3% 0.0 VNOM VNOM + 3% 3.0 mA A V IVIDEOQS 30 45 IVIDEOSHT ILMAX+20 % A VVIDEOLIPP 5.0 8.0 mA VVIDEOLOPP 0.20 mV VVIDEO VNOM - 3% VNOM VNOM + 3% mV/mA V ESRVIDEO 20 100 COVIDEO 1.1 2.2 m VINVIDEO IVIDEO VNOM+0.2 5 0 UVDET -4.65 250/350 4.65 V mA V F Symbol Min Typ Max Unit
13892
Analog Integrated Circuit Device Data Freescale Semiconductor
17
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (Continued) Currents valid over entire operating temperature range, except at 25C only. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included.
Characteristic VAUDIO ACTIVE MODE DC Output Voltage VOUT (VINMIN < VIN < VINMAX, ILMIN < IL < ILmax) Load Regulation (1.0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX) Line Regulation VINMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short circuit VOUT to GND Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 VPLL AND VDIG Operating Input Voltage Range VINMIN to VINMAX VDIG, VPLL all settings, BP biased VPLL, VDIG [1:0] = 00,01 VPLL, VDIG [1:0] = 10, 11, External Switcher Operating Current Load Range ILMIN to ILMAX Minimum Bypass Capacitor Value Used as a condition for all other parameters Bypass Capacitor ESR 10 kHz -1.0 MHz VPLL AND VDIG ACTIVE MODE DC (ONLY FOR 2.475, 2.7, AND 2.775 STEPS) Output Voltage VOUT VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX Load Regulation 1.0 mA < IL < ILMAX for any VINMIN < VIN < VINMAX Line Regulation VINMIN < VIN < VINMAX for any ILMIN < IL < ILMAX Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 VIOHI Operating Input Voltage Range VINMIN to VINMAX VNOM = 2.775 V Operating Current Load Range ILMIN to ILMAX Extended Input Voltage Range (Performance may be out of specification) Minimum Bypass Capacitor Value Bypass Capacitor ESR 10 kHz -1.0 MHz 13892 IIOHI VINIOHIEXT COIOHI ESRIOHI 0 100 VINIOHI VNOM+0.2 5 0 UVDET 0.65 2.2 4.65 100 4.65 mA V F m V VPLLLOR, VDIGLOR VPLLLIR, VDIGLIR IPLLLQS, IDIGLQS VPLL, VDIG VNOM - 0.05 VNOM VNOM + 0.05 mV/mA 0.35 mV 5.0 8.0 A 8.0 10.5 V IPLL, IDIG COPLL, CODIG ESRPLL, ESRDIG VINPLL, VINDIG V UVDET 1.75 2.15 0 SW4 = 1.8 2.2 50 mA F 0.65 2.2 0 0.1 4.65 4.65 4.65 IAUDIOQS 8.0 10.5 IAUDIOSHT ILMAX+20 % A VAUDIO VAUDIOLOR VAUDIOLIR 5.0 8.0 mA VNOM - 3% VNOM VNOM + 3% 0.25 V mV/mA mV Symbol Min Typ Max Unit
18
Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (Continued) Currents valid over entire operating temperature range, except at 25C only. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included.
Characteristic VIOHI ACTIVE MODE DC Output Voltage VOUT - (VNOM = 2.775) VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX Load Regulation 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 VCAM Operating Input Voltage Range VINMIN to VINMAX Operating Current Load Range ILMIN to ILMAX Internal pass FET External PNP Extended Input Voltage Range Performance may be out of specification Minimum Bypass Capacitor Value Internal pass device External PNP (not exceeding PNP max power) Bypass Capacitor ESR 10 kHz -1.0 MHz VCAM ACTIVE MODE DC Output Voltage VOUT (VNOM = 2.775) VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX Load Regulation 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0, Internal PMOS configuration VINMIN < VIN < VINMAX, IL = 0, External PNP configuration ICAMQS 25 30 35 45 ICAMSHT ILMAX+20 % A VCAMLIR 5.0 8.0 mA VCAMLOR 0.25 mV VCAM VNOM - 3% VNOM VNOM + 3% mV/mA V ESRCAM 20 100 COCAM 0.65 1.1 2.2 2.2 m VINCAMEXT UVDET 4.65 F VINCAM ICAM 0 0 65 250 VNOM +0.25 4.65 V mA IIOHQS 8.0 10.5 VIOHLIR 5.0 8.0 A VIOHLOR 0.35 mV VIOH VNOM - 3% VNOM VNOM + 3% mV/mA V Symbol Min Typ Max Unit
13892
Analog Integrated Circuit Device Data Freescale Semiconductor
19
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (Continued) Currents valid over entire operating temperature range, except at 25C only. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included.
Characteristic VCAM LOW POWER MODE DC Output Voltage VOUT VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP Current Load Range ILMINLP to ILMAXLP Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 VSD Operating Input Voltage Range VINMIN to VINMAX VSD[2:0]=010 to 111 VSD[2:0]=010 to 111, Extended Operation VSD[2:0]=000, 001 [000] BP Supplied VSD[2:0]=000 External Switcher Supplied Operating Current Load Range ILMIN to ILMAX Not exceeding PNP max power Extended Input Voltage Range Performance may be out of specification for output levels VSD[2:0]=010 or greater Minimum Bypass Capacitor Value Bypass Capacitor ESR 10 kHz -1.0 MHz VSD ACTIVE MODE DC Output Voltage VOUT VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX Load Regulation 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 ISDQS 30 45 ISDSHT ILMAX+20 % A VSDLIR 5.0 8.0 mA VSDLOR 0.25 mV VSD VNOM - 3% VNOM VNOM + 3% mV/mA V COSD ESRSD 20 100 VINSDEXT UVDET 1.1 2.2 4.65 F m ISD 0 250 V VINSD VNOM+0.2 5 UVDET UVDET 2.15 mA 2.20 4.65 4.65 4.65 4.65 V ICAMLO ICAMQSLO 8.0 10.5 VCAMLO VNOM - 3% 0 VNOM VNOM + 3% 3.0 mA A V Symbol Min Typ Max Unit
13892
20
Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (Continued) Currents valid over entire operating temperature range, except at 25C only. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included.
Characteristic VSD LOW POWER MODE DC - VSDMODE=1 Output Voltage VOUT VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP Current Load Range ILMINLP to ILMAXLP Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 VUSB GENERAL Operating Input Voltage Range VINMIN to VINMAX Supplied by VBUS Supplied by SWBST Operating Current Load Range ILMIN to ILMAX Bypass Capacitor Value Range Bypass Capacitor ESR 10 kHz -1.0 MHz VUSB ACTIVE MODE DC Output Voltage VOUT VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX Load Regulation 0 < IL < ILMAX from DM/DP for any VINMIN < VIN < VINMAX Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND VUSB2 Operating Input Voltage Range VINMIN to VINMAX Extended operation Operating Current Load Range ILMIN to ILMAX Minimum Bypass Capacitor Value Used as a condition for all other parameters Bypass Capacitor ESR 10 kHz -1.0 MHz ESRUSB2 0 0.1 IUSB2 COUSB2 0.65 2.2 VINUSB2 VNOM +0.25 UVDET 0 4.65 4.65 50 mA F V VUSBSHT ILMAX+20 % VUSBLIR 20 mA VUSBLOR 1.0 mV VUSB VNOM - 4% 3.3 VNOM + 4% mV/mA V IUSB COUSB ESRUSB 0 0.1 VINUSB 4.4 0 0.65 5.0 2.2 5.25 5.75 100 mA F V ISDLO ISDQSLO 8.0 10.5 VSDLO VNOM - 3% 0 VNOM VNOM + 3% 3.0 mA A V Symbol Min Typ Max Unit
13892
Analog Integrated Circuit Device Data Freescale Semiconductor
21
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (Continued) Currents valid over entire operating temperature range, except at 25C only. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included.
Characteristic VUSB2 ACTIVE MODE DC Output Voltage VOUT VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX Load Regulation 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 UVBUS Operating Input Voltage Range VINMIN to VINMAX(11) UREGIN supplied by SWBST Operating Current Load Range ILMIN to ILMAX Minimum Bypass Capacitor Value Bypass Capacitor ESR 10 kHz -1.0 MHz UVBUS ACTIVE MODE DC Output Voltage Vout - (VNOM = 2.775) VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX VGEN1 Operating Input Voltage Range VINMIN to VINMAX All settings, BP biased VINGEN1 UVDET < VNOM +0.25 1.75 IGEN1 0 UVDET COGEN1 ESRGEN1 20 100 0.65 2.2 200 V 4.65 +35% F m 4.65 V VUVBUS 4.4 5.0 5.25 V IUVBUS COUVBUS VINUVBUS
(21) (21) (22)
Symbol
Min
Typ
Max
Unit
VUSB2 VNOM - 3% VUSB2LOR VUSB2LIR IUSB2QS 8.0 13 5.0 8.0 0.35 VNOM VNOM + 3%
V
mV/mA
mV
A
VINUVBUS 4.75 0
(21)
V 5.0 (21)
5.25 100 6.5
(22)
mA F
VGEN1=00,01, External switcher supplied Operating Current Load Range ILMIN to ILMAX (not exceeding PNP max power) Extended input voltage range (BP biased, performance may be out of specification for output levels VGEN1[1:0]=10 to 11) Minimum Bypass Capacitor Value Bypass Capacitor ESR 10 kHz -1.0 MHz
SW4 = 1.8
4.65 mA
Notes 21. Filtering is shared with CHRGRAW (shorted at board level). 2.2 F is typically included at the CHRGRAW pin. 22. 6.5 F is the maximum allowable capacitance on VBUS including all tolerances of filtering capacitance on VBUS and CHRGRAW (which are shorted at the board level).
13892
22
Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (Continued) Currents valid over entire operating temperature range, except at 25C only. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included.
Characteristic VGEN1 ACTIVE MODE DC Output Voltage VOUT VGEN1=00, 01, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX VGEN1=10, 11, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX Load Regulation 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 VGEN1 LOW POWER MODE DC - VGEN1MODE=1 Output Voltage VOUT - VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP VGEN1=00, 01 VGEN1=10, 11 Current Load Range ILMINLP to ILMAXLP Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 VGEN2 GENERAL Operating Input Voltage Range VINMIN to VINMAX All settings, BP biased VINGEN2 UVDET< VNOM+0.2 5 2.15 IGEN2 0 UVDET COGEN2 ESRGEN2 20 100 1.1 2.2 2.2 4.65 4.65 350 4.65 +35% F m mA V V IGEN1LO IGEN1QSLO 8.0 10.5 VGEN1LO VNOM - 0.05 VNOM - 3% 0 VNOM VNOM VNOM + 0.05 VNOM + 3% 3.0 mA A V IGEN1QS 20 45 VGEN1SHT ILMAX+20 % A VGEN1LIR 5.0 8.0 mA VGEN1LOR 0.25 mV VGEN1 VNOM - 0.05 VNOM - 3% VNOM VNOM VNOM + 0.05 VNOM + 3% mV/mA V Symbol Min Typ Max Unit
VGEN2=000,001, External switcher supplied Operating Current Load Range ILMIN to ILMAX (Not exceeding PNP max power) Extended input voltage range (BP biased, performance may be out of specification for output levels VGEN2[2:0]=100 to 111) Minimum Bypass Capacitor Value Bypass Capacitor ESR 10 kHz -1.0 MHz
13892
Analog Integrated Circuit Device Data Freescale Semiconductor
23
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (Continued) Currents valid over entire operating temperature range, except at 25C only. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included.
Characteristic VGEN2 ACTIVE MODE DC Output Voltage VOUT VGEN2=000, 001, 010, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX VGEN2=011, 100, 101, 110, 111, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX Load Regulation 1.0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX Line Regulation VINMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 VGEN2 LOW POWER MODE DC - VGEN2MODE=1 Output Voltage VOUT - VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP VGEN2=000 to 010 VGEN2=011 to 111 Current Load Range ILMINLP to ILMAXLP Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 VGEN3 GENERAL Operating Input Voltage Range VINMIN to VINMAX VGEN3CONFIG, VGEN3=01, 11 VGEN3CONFIG, VGEN3=00, 10 Operating Current Load Range ILMIN to ILMAX Internal Pass FET External PNP (Not exceeding PNP max power) Minimum Bypass Capacitor Value Internal pass device External pass device Bypass Capacitor ESR 10 kHz -1.0 MHz ESRGEN3 20 100 COGEN3 0.65 1.1 2.2 2.2 m IGEN3 0 0 50 200 F VINGEN3 VNOM+0.2 UVDET 4.65 4.65 mA V IGEN2LO IGEN2QSLO 8.0 10.5 VGEN2LO VNOM - 0.05 VNOM - 3% 0 VNOM VNOM VNOM + 0.05 VNOM + 3% 3.0 mA A V IGEN2QS 35 45 VGEN2SHT ILMAX+20 % uA VGEN2LIR 5.0 8.0 mA VGEN2LOR 0.20 mV VGEN2 VNOM - 0.05 VNOM - 3% VNOM VNOM VNOM + 0.05 VNOM + 3% mV/mA V Symbol Min Typ Max Unit
13892
24
Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (Continued) Currents valid over entire operating temperature range, except at 25C only. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included.
Characteristic VGEN3 ACTIVE MODE DC Output Voltage VOUT VGEN2=000, 001, 010, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX Load Regulation 1.0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX Line Regulation VINMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX VGEN3 ACTIVE MODE DC (CONTINUED) Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short circuit VOUT to GND Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0, Internal PMOS configuration VINMIN < VIN < VINMAX, IL=0, external PNP configuration VGEN3 LOW POWER MODE DC Output Voltage VOUT - (Accuracy) VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP Current Load Range ILMINLP to ILMAXLP Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 CHARGE PATH REGULATOR Input Operating Voltage - CHRGRAW Output Voltage Trimming Accuracy VCHRG[2:0]=011, Charge current 50 mA at T=25C Output Voltage Spread - VCHRG[2:0]=011, 1XX Charge current 1.0 mA to 100 mA Charge current 100 mA and above Current Limit Tolerance ICHRG[3:0]=0001 ICHRG[3:0]=0100 ICHRG[3:0]=0110
(23)
Symbol
Min
Typ
Max
Unit
VGEN3 VNOM - 3% VGEN3LOR VGEN3SHT 5.0 8.0 0.40 VNOM VNOM + 3%
V
mV/mA
mV
VGEN3SHT ILMAX+20 % IGEN3QS 25 30 35 45 -
mA
A
VGEN3LO VNOM-3% IGEN3LO IGEN3QSLO 8.0 10.5 0 VNOM 1.0 VNOM+3% 3.0
V
mA A
VINCHRG BPTRIM
BATTMIN -
-
20
V %
-
0.35 %
BPSP -1.0 -3.0 ILIM 68 360 500 BPOS-START 80 400 560 92 440 620 15 2.0 1.0 1.0
mA mA mA % %
All other settings
Start-up Overshoot - Unloaded Notes 23. Excludes spread and tolerance due to board and 100 mOhm sense resistor tolerances.
13892
Analog Integrated Circuit Device Data Freescale Semiconductor
25
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (Continued) Currents valid over entire operating temperature range, except at 25C only. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included.
Characteristic CHARGE PATH REGULATOR (CONTINUED) Transient Overshoot Charge current 1.0 mA to 1.0 A, Rise time 5.0 us Configuration Input Capacitance - CHRGRAW(24) Load Capacitor - BPSNS Cable length THERMAL Thermal Warning Lower Threshold Thermal Warning Higher Threshold Thermal Warning Hysteresis(25) TWL TWH TWHY TPT 95 115 2.0 130 100 120 140 105 125 4.0 150 C C C C
(24)
Symbol
Min
Typ
Max
Unit
BPOS
-
-
2.0
%
CINCHRG CBP LC
10 -
2.2 -
47 3
F F m
Thermal Protection Threshold BACKLIGHT LED DRIVERS Absolute Accuracy - All current settings Matching - At 400 mV, 21 mA Leakage - LEDxDC[5:0]=000000 SIGNALING LED DRIVERS Absolute Accuracy - All current settings Matching - At 400 mV, 21 mA Leakage - LEDxDC[5:0]=000000 UVBUS - GENERAL Operating Input Voltage Range VINMIN to VINMAX(26) VINUSB supplied by SWBST Operating Current Load Range ILMIN to ILMAX Minimum Bypass Capacitor Value Bypass Capacitor ESR - 10 kHz-1.0 MHz ACTIVE MODE DC Output Voltage VOUT - (VNOM = 2.775), VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX Short-circuit Protection Threshold ** - VINMIN < VIN < VINMAX, Short-circuit VOUT to ground Notes 24. 25. 26. 27. 28.
-
-
15 3 1
% % A
-
-
15 3 1
% % A
V 4.75 0
(27) (27) (27) (27)
5
5.25 100 6.5
(28)
mA F W
(28)
4.4 ILMAX+20 %
5.0 -
5.25 -
V mA
An additional derating of 35% is allowed. Equivalent to approx. 30 mW min, 60 mW max Guaranteed by design. Filtering is shared with CHRGRAW (shorted at board level). 2.2 uF is typically included at the CHRGRAW pin. 6.5 uF is the maximum allowable capacitance on VBUS including all tolerances of filtering capacitance on VBUS and CHRGRAW (which are shorted at the board level).
13892
26
Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (Continued) Currents valid over entire operating temperature range, except at 25C only. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included.
Characteristic ADC Conversion Current Converter Core Input Range Single ended voltage readings Differential readings Maximum Input Voltage(29) Channels ADIN5, ADIN6 and ADIN7 Integral Nonlinearity Differential Nonlinearity Zero Scale Error (Offset) Before auto calibration After auto calibration Full Scale Error (Gain) Before auto calibration After auto calibration Drift Over-temperature Source Impedance No bypass capacitor at input Bypass capacitor at input 10 nF Input Buffer Offset - BUFFEN=1 Input Buffer Range - BUFFEN=1 Notes 29. ADIN5, 6 and 7 inputs must not exceed BP voltage. 30. Guaranteed by design. -5 0.02 5 30 5 2.4 mV V
(30)
Symbol
Min
Typ
Max
Unit
1
mA V
0 -1.2
2.4 1.2 BP V
3 1
LSB LSB LSB
10 1 LSB 25 5 - Including scaling 1 LSB K
13892
Analog Integrated Circuit Device Data Freescale Semiconductor
27
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (Continued) Currents valid over entire operating temperature range, except at 25C only. Current in RTC Mode is from LICELL = 2.5 V, in all other modes from BP = 3.6 V. External loads are not included.
Characteristic TOUCH SCREEN Plate Maximum Voltage X, Y(32) Plate Resistance X, Y Resistance Between Plates Setting Time - Contact Position measurement Capacitance Between Plates Contact Resistance Current Source Interrupt Current Source Interrupt Threshold for Pressure Application Interrupt Threshold for Pressure Removal Current Source Inaccuracy - Over-temperature Touch Screen Quiescent Current - Active Mode Max Load Current - Active Mode Output Voltage - 0(33)
Symbol
Min
Typ
Max
Unit
VCORE 100 180 3 0.5 2 100 20 40 60 50 80 60 95 20 1000 1200 5.5
V s nF uA uA K K %
20 20 -3% 1.20 +3% 0.8 40 0 0.65 2.2 100 0.1 +35%
A mA V mV/mA dB F
- IL=15 mA
Bypass Capacitor ESR Bypass Capacitance Discharge Resistor - Regulator disable Notes 31. All characteristics in this table are applicable only for non touch screen operation 32. TS[xy][1,2] inputs must not exceed BP or VCORE 33. Guaranteed by design.
13892
28
Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V BATT 4.8 V, --30 TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic 32X CRYSTAL OSCILLATOR RTC oscillator start-up time Upon application of power CLK32K Rise and Fall Time - CL=50 pF CLK32KDRV[1:0]=00 (default) CLK32KDRV[1:0]=01 CLK32KDRV[1:0]=10 CLK32KDRV[1:0]=11 CLK32KMCU Rise and Fall Time CL=12 pF CLK32K and CLK32KMCU Output Duty Cycle Crystal on XTAL1, XTAL2 pins RMS Output Jitter(34) 1.0 Sigma for Gaussian distribution CLK AND MISO MISO Rise and Fall Time, CL=50 pF, SPIVCC=1.8 V SPIDRV [1:0]=00 (default) SPIDRV [1:0]=01 SPIDRV [1:0]=10 SPIDRV [1:0]=11 BUCK CONVERTERS Turn-on Time, Enable to 90% of end value, IL=0 SWBST Turn-on Time Enable to 90% of VOUT, IL=0 Transient Load Response, IL from 1.0 mA to 100 mA in 1.0 s steps Maximum transient Amplitude Time to settle 80% of transient Transient Load Response, IL from 100 mA to 1.0 mA Maximum transient Amplitude Time to settle 80% of transient Notes 34. Output jitter exhibits a Gaussian distribution ATMAX 300 20 mV s ATMAX 300 500 mV s tONBST 2.0 ms tONPWM 500 s tMISOET 11 6.0 High Z 22 ns tCLK32KMCUE
T
Symbol
Min
Typ
Max
Unit
tRTCST tCLK32KET 22 11 High Z 44 1.0
Sec
ns
ns 22 % 45 55 ns RMS 30
tCLK32KDC, tCLK32KMCUD
C
tCLKJ
13892
Analog Integrated Circuit Device Data Freescale Semiconductor
29
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V BATT 4.8 V, --30 TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic SWLEDOUT Switching Frequency(35) PLLx[2:0] = 100 Start-up Time VVIDEO ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV VIN = VNOM + 1.0 V Output Noise - VIN = VINMIN, IL = 75% of ILMAX 100 Hz - 1.0 kHz >1.0 kHz - 10 kHz >10 kHz - 1.0 MHz Spurs 32.768 kHz and harmonics Turn-on Time Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 Turn-off Time Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 Transient Load Response VIN = VINMIN, VINMAX VVIDEOTLOR 1.0 2.0 VVIDEOOS 1.0 2.0 % VVIDEOtOFF 0.1 10 % VVIDEOtON 1.0 ms VVIDEOSP -120 ms VVIDEOON -114 -124 -129 dB VVIDEOPSS R dB 35 50 40 60 dBV/Hz tST fSWLED 2.097 100 s MHz Symbol Min Typ Max Unit
Notes 35. The switcher runs at 2/3 of the buck switcher PLL frequency and follows the PLL[2:0] programming.
13892
30
Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V BATT 4.8 V, --30 TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic VVIDEO ACTIVE MODE - AC (CONTINUED) Transient Line Response IL = 75% of ILMAX Mode Transition Time From low power to active, VIN = VINMIN, VINMAX, IL =ILMAXLP Mode Transition Response(36) From low power to active and from active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV, > UVDET VIN = VNOM + 1.0 V, > UVDET Output Noise - VIN = VINMIN, IL = 0.75*ILmax 100 Hz - 1.0 kHz >1.0 kHz - 10 kHz >10 kHz - 1.0 MHz Spurs 32.768 kHz and harmonics Turn-on Time Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 Turn-off Time Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 Transient Load Response - See Transient Response Waveforms on page 56, VIN = VINMIN, VINMAX Transient Line Response - See Transient Response Waveforms on page 56 IL = 75% of ILMAX VPLL AND VDIG ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = UVDET VIN = VNOM + 1.0 V, > UVDET Output Noise - VIN = VINMIN, IL = 0.75*ILMAX 100 Hz - 1.0 kHz >1 kHz - 1.0 MHz Spurs 32.768 kHz and harmonics Notes 36. Guaranteed by design. VPLLSP -85 VPLLON 20 2.5 dB/dec V/Hz dB VPLLPSSR 35 50 40 60 dB VAUDIOTLOR VAUDIOTLIR 5.0 8.0 1.0 2.0 mV VAUDIOOS 1.0 2.0 % VAUDIOtOFF 0.1 10 % VAUDIOtON 1.0 ms VAUDIOSP -120 ms VAUDIOON -114 -124 -129 dB VAUDIOPSS R VVIDEOtMOD
+
Symbol
Min
Typ
Max
Unit
VVIDEOTLIR 5.0 8.0
mV
s 100 % 1.0 2.0 dB 35 50 40 60 dBV/Hz
VVIDEOMTR
13892
Analog Integrated Circuit Device Data Freescale Semiconductor
31
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V BATT 4.8 V, --30 TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic VPLL AND VDIG ACTIVE MODE - AC (CONTINUED) Turn-on Time Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 Turn-off Time Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 Transient Load Response - See Transient Response Waveforms on page 56 VIN = VINMIN, VINMAX Transient Line Response - See Transient Response Waveforms on page 56 IL = 75% of ILMAX VIOHI ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV, > UVDET VIN = VNOM + 1.0 V, > UVDET Output Noise - VIN = VINMIN, IL = 0.75*ILMAX 100 Hz - 1.0 kHz >1.0 kHz - 1.0 MHz Spurs 32.768 kHz and harmonics Turn-on Time Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 Turn-off Time Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 Transient Load Response - See Transient Response Waveforms on page 56 VIN = VINMIN, VINMAX Transient Line Response - See Transient Response Waveforms on page 56 IL = 75% of ILMAX Mode Transition Time - See Transient Response Waveforms on page 56 From low power to active, VIN = VINMIN, VINMAX, IL = ILMAXLP Mode Transition Response From low power to active and from active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP VIOHIMTR 1.0 2.0 VIOHIMTR 10 % VIOHITLIR 5.0 8.0 s VIOHITLOR 1.0 2.0 mV VIOHIOS 1.0 2.0 % VIOHItOFF 0.1 10 % VIOHItON 1.0 ms VIOHISP -100 ms VIOHION 20 1.0 dB/dec V/Hz dB VIOHIPSSR 35 50 40 60 dB VPLLOS, VDIGOS VPLLTLOR, VDIGTLOR VPLLTLIR, VDIGTLIR VPLLtOFF 0.1 1.0 2.0 10 2.0 4.0 % % mV 50 70 mV 5.0 8.0 VPLLtON 100 ms s Symbol Min Typ Max Unit
13892
32
Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V BATT 4.8 V, --30 TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic VCAM ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV VIN = VNOM + 1.0 V Output Noise - VIN = VINMIN, IL = 0.75*ILMAX 100 Hz - 1.0 kHz >1.0 kHz - 1.0 MHz Spurs 32.768 kHz and harmonics Turn-on Time (Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0) Turn-off Time (Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0) Start-up Overshoot (VIN = VINMIN, VINMAX, IL = 0) Transient Load Response - See Transient Response Waveforms on page 56 VIN = VINMIN, VINMAX VCAM=01, 10, 11 VCAM=00 Transient Line Response - See Transient Response Waveforms on page 56 IL = 75% of ILMAX Mode Transition Time - See Transient Response Waveforms on page 56 From low power to active, VIN = VINMIN, VINMAX, IL = ILMAXLP Mode Transition Response From low power to active and from, active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP VSD ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV VIN = VNOM + 1.0 V Output Noise - VIN = VINMIN, IL = 75% of ILMAX 100 Hz - 1.0 kHz >1.0 kHz - 10 kHz >10 kHz - 1.0 MHz Spurs (32.768 kHz and harmonics) Turn-on Time (Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0) Turn-off Time (Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0) Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 VSDSP VSDtON VSDtOFF VSDOS 1.0 2.0 VSDON 0.1 -115 -126 -132 -100 1.0 10 dB ms ms % VSDPSSR 35 50 40 60 dBV/Hz dB VCAMMTR 1.0 2.0 VCAMtMOD 100 % VCAMLIR 5.0 8.0 s 1.0 50 2.0 70 % mV mV VCAMtON VCAMtOFF VCAMOS VCAMLOR VCAMSP 0.1 1.0 -100 1.0 10 2.0 ms ms % VCAMON 20 1.0 dB/dec V/Hz dB VCAMPSSR 35 50 40 60 dB Symbol Min Typ Max Unit
13892
Analog Integrated Circuit Device Data Freescale Semiconductor
33
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V BATT 4.8 V, --30 TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic VSD ACTIVE MODE - AC (CONTINUED) Transient Load Response - See Transient Response Waveforms on page 56 VIN = VINMIN, VINMAX - VSD[2:0]=010 to 111 - VSD[2:0]=000 to 001 Transient Line Response - See Transient Response Waveforms on page 56 IL = 75% of ILMAX Mode Transition Time - See Transient Response Waveforms on page 56 From low power to active, VIN = VINMIN, VINMAX, IL = ILMAXLP Mode Transition Response - See Transient Response Waveforms on page 56 From low power to active and from active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP VUSB ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV Output Noise - VIN = VINMIN, IL = 75% of ILMAX 100 Hz - 50 kHz >50 kHz - 1.0 MHz VUSB2 ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV VIN = VNOM + 1.0 V Output Noise - VIN = VINMIN, IL = 0.75*ILMAX 100 Hz - 1.0 kHz >1.0 kHz - 1.0 MHz Spurs 32.768 kHz and harmonics Turn-on Time(37) Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 Turn-off Time
(37)
Symbol
Min
Typ
Max
Unit
VSDTLOR VSDTLIR VSDtMOD VSDMTR 1.0 2.0 100 % 5.0 8.0 s 1.0 2.0 70 % mV mV
VUSBPSSR 35 VUSBON 1.0 0.2 40 -
dB
V/Hz
VUSB2PSSR 35 50 VUSB2ON VUSB2SP VUSB2tON VUSBtOFF 0.1 VUSB2OS VUSB2TLOR VUSB2TLIR 5.0 8.0 1.0 2.0 1.0 2.0 10 100 -100 20 0.2 40 60 -
dB
dB/dec V/Hz dB
s
ms
Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 Transient Load Response - See Transient Response Waveforms on page 56 VIN = VINMIN, VINMAX Transient Line Response - See Transient Response Waveforms on page 56 IL = 75% of ILMAX Notes 37. Guaranteed by design.
%
%
mV
13892
34
Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V BATT 4.8 V, --30 TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic UVBUS ACTIVE MODE DC Turn-on Time(38) VBUS Rise Time per USB OTG with max loading of 6.5 F+10 F Turn-off Time(38) Disable to 0.8 V, per USB OTG specification parameter VA_SESS_VLD, VIN = VINMIN, VINMAX, IL=0 VGEN1 ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = UVDET VIN = VNOM + 1.0 V, > UVDET Output Noise - VIN = VINMIN, IL = 0.75*ILMAX 100 Hz - 1.0 kHz >1.0 kHz - 10 kHz >10 kHz - 1.0 MHz Spurs 32.768 kHz and harmonics Turn-on Time Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0 Turn-off Time Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 Transient Load Response - See Transient Response Waveforms on page 56 VIN = VINMIN, VINMAX - VGEN1[1:0]=10 to 11 - VGEN[1:0]=00 to 01 Transient Line Response - See Transient Response Waveforms on page 56 IL = 75% of ILMAX Mode Transition Time - See Transient Response Waveforms on page 56 From low power to active VIN = VINMIN, VINMAX, IL = ILMAXLP Mode Transition Response - See Transient Response Waveforms on page 56 From low power to active and from active to low power VIN = VINMIN, VINMAX, IL = ILMAXLP Notes 38. Guaranteed by design. VGEN1MTR 1.0 2.0 VGEN1tMOD 100 % VGEN1TLIR 5.0 8.0 s 1.0 2.0 70 % mV mV VGEN1TLOR VGEN1OS 1.0 2.0 VGEN1tOFF 0.1 10 % VGEN1tON 1.0 ms VGEN1SP -100 ms VGEN1ON -115 -126 -132 dB VGEN1PSS R dB 35 50 40 60 dBV/Hz UVBUStOFF 1.3 UVBUStON 100 sec ms Symbol Min Typ Max Unit
13892
Analog Integrated Circuit Device Data Freescale Semiconductor
35
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V BATT 4.8 V, --30 TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic VGEN2 ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV VIN = VNOM + 1.0 V Output Noise - VIN = VINMIN, IL = ILMAX 100 Hz - 1.0 kHz >1.0 kHz - 10 kHz >10 kHz - 1.0 MHz Spurs (32.768 kHz and harmonics) Turn-on Time Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0 Turn-off Time (Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0) VGEN2 ACTIVE MODE - AC Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 Transient Load Response(39) - See Transient Response Waveforms on page 56 VIN = VINMIN, VINMAX - VGEN2[2:0]=100 to 111 - VGEN2[2:0]=000 to 011 Transient Line Response - See Transient Response Waveforms on page 56 IL = 75% of ILMAX Mode Transition Time - See Transient Response Waveforms on page 56 From low power to active VIN = VINMIN, VINMAX, IL = ILMAXLP Mode Transition Response - See Transient Response Waveforms on page 56 From low power to active and from active to low power VIN = VINMIN, VINMAX, IL = ILMAXLP VGEN3 ACTIVE MODE - AC PSRR IL = 75% of ILMAX, 20 Hz to 20 kHz, VIN = VINMIN +100 mV Vin=Vnom+1V Output Noise - VIN = VINMIN, IL = 75% of ILMAX 100 Hz - 1.0 kHz >1.0 kHz - 1.0 MHz Spurs 32.768 kHz and harmonics Notes 39. Guaranteed by design. VGEN3SP -100 VGEN3ON 20 1.0 dB/dec V/Hz dB VGEN3PSS R dB 35 45 40 50 VGEN2MTR 1.0 2.0 VGEN2tMOD 100 % VGEN2TLIR 5.0 8.0 s 1.0 3.0 70 % mV mV VGEN2TLOR VGEN2OS 1.0 2.0 % VGEN2tOFF VGEN2SP VGEN2tON 0.1 1.0 10 ms VGEN2ON -115 -126 -132 -100 dB ms VGEN2PSS R dB 35 50 40 60 dBV/Hz Symbol Min Typ Max Unit
13892
36
Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V BATT 4.8 V, --30 TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic VGEN3 ACTIVE MODE - AC (CONTINUED) Turn-on Time Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0 Turn-off Time Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 Transient Load Response VIN = VINMIN, VINMAX - VGEN3=1 - VGEN3=0 Transient Line Response (IL = 75% of ILMAX) Mode Transition Time From low power to active VIN = VINMIN, VINMAX, IL = ILMAXLP Mode Transition Response From low power to active and from active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP UVBUS - ACTIVE MODE DC Turn-On Time (40) - VBUS Rise Time por USB OTG with max loading of 6.5 F+10 F Turn-Off Time (40) - Disable to 0.8 V, per USB OTG specification parameter VA_SESS_VLD VIN = VINMIN, VINMAX, IL=0 ADC Conversion Time per Channel - PLLX[2:0]=100 Turn On Delay If Switcher PLL was active If Switcher PLL was inactive TOUCH SCREEN Turn-on Time (40) - 90% of output Notes 40. Guaranteed by design. 500 s 0 5 10 10 s s 100 1.3 ms sec VGEN3MTR 1.0 2.0 VGEN3TLIR VGEN3tMOD 100 % 1.0 5.0 2.0 70 8.0 % mV mV s VGEN3TLOR VGEN3OS 1.0 2.0 VGEN3tOFF 0.1 5.0 % VGEN3tON 1.0 ms ms Symbol Min Typ Max Unit
13892
Analog Integrated Circuit Device Data Freescale Semiconductor
37
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
Figure 5 and Table 7 summarize the SPI electrical and timing requirements. The SPI input and output levels are set independently via the SPIVCC pin by connecting it to the desired supply. This would typically be tied to SW4 programmed for 1.80 V. The strength of the MISO driver is programmable through the SPIDRV[1:0] bits.
CS
TCLKPER TCLKHIGH TCLKLOW TSELSU TSELHLD TSELLOW
CLK
TWRTSU
TWRTHLD
MOSI
TRDEN
TRDSU
TRDHLD
TRDDIS
MISO
Figure 5. Timing Requirements Table 7. Timing Parameter Description
PARAMETER tSELSU tSELHID tSELLOW tCLKPER tCLKHIGH tCLKLOW tWRTSU tWRTHLD tRDSU tRDHLD tRDEN tRDDIS DESCRIPTION Time CS has to be high before the first rising edge of CLK Time CS has to remain high after the last falling edge of CLK Time CS has to remain low between two transfers Clock period of CLK Part of the clock period where CLK has to remain high Part of the clock period where CLK has to remain low Time MOSI has to be stable before the next rising edge of CLK Time MOSI has to remain stable after the rising edge of CLK Time MISO will be stable before the next rising edge of CLK Time MISO will remain stable after the falling edge of CLK Time MISO needs to become active after the rising edge of CS Time MISO needs to become inactive after the falling edge of CS T MIN (NS) 15 15 15 38 15 15 4.0 4.0 4.0 4.0 4.0 4.0
Notes 41. This table reflects a maximum SPI clock frequency of 26 MHz. Slew rate for SPI MISO output driver is programmable from 0.16 to 0.66 V/ns
13892
38
Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION FUNCTIONAL PIN DESCRIPTION CHARGER CHRGRAW
1. Charger input. The charger voltage is measured through an ADC at this pin. The UVBUS pin must be shorted to CHRGRAW in cases where the charger is being supplied from the USB cable. The minimum voltage for this pin depends on BATTMIN threshold value (see Battery Management). 2. Output to battery supplied accessories. The battery voltage can be applied to an accessory by enabling the charge path for the accessory via the CHRGRAW pin. To accomplish this, the charger needs to be configured in reverse supply mode.
BATTISNS
Battery current sensing point 1. The current flowing out of and into the battery can be read via the ADC by monitoring the voltage drop over the sense resistor between BATT and BATTISNS.
BATT
Battery positive terminal. Battery current sensing point 2. The supply voltage of the battery is sensed through an ADC on this pin. The current flowing out of and into the battery can be read via the ADC by monitoring the voltage drop over the sense resistor between BATT and BATTISNS.
BATTISNSCC
Accumulated current counter current sensing point. This is the coulomb counter current sense point. It should be connected directly to the 0.020 sense resistor via a separate route from BATTISNS. The coulomb counter monitors the current flowing in/out of the battery by integrating the voltage drop over the BATTISNCC and the BATT pin.
CHRGCTRL1
Driver output for charger path FET M1.
CHRGCTRL2
Driver output for charger path FET M2.
CHRGISNS
Charge current sensing point 1. The charge current is read by monitoring the voltage drop over the charge current 100 m sense resistor connected between CHRGISNS and BPSNS.
CFP AND CFM
Accumulated current filter cap plus and minus terminals respectively. The coulomb counter will require a 10 F output capacitor connected between these pins to perform a first order filtering of the signal across R1.
BPSNS
1. BP sense point. BP voltage is sensed at this pin and compared with the voltage at CHRGRAW. 2. Charge current sensing point 2. The charge current is read by monitoring the voltage drop over the charge current 100 m sense resistor. This resistor is connected between CHRGISNS and BPSNS.
CHRGSE1B
An unregulated wall charger configuration can be built in which case this pin must be pulled low. When charging through USB, it can be left open since it is internally pulled up to VCORE. The recommendation is to place an external FET that can pull it low or left it open, depending on the charge method.
BP
This pin is the application supply point, the input supply to the IC core circuitry. The application supply voltage is sensed through an ADC at this pin.
CHRGLED
Trickle LED driver output 1. Since normal LED control via the SPI bus is not always possible in the standalone operation, a current sink is provided at the CHRGLED pin. This LED is to be connected between this pin and CHRGRAW.
BATTFET
Driver output for battery path FET M3. If no charging system is required, the pin BATTFET must be floating. When single path is implemented, it must be connected to ground.
GNDCHRG
Ground for charger interface.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
LED DRIVERS SWLEDOUT
Boost converter output for serial LED drive. It provides up to 25.5 V for supplying LED strings driven by LEDMD, LEDAD and LEDKP.
GNDCORE
Ground for the IC core circuitry.
POWER GATING PWGTDRV1 AND PWGTDRV2
Power Gate Drivers. PWGTDRV1 is provided for power gating peripheral loads sharing the processor core supply domain(s) SW1, and/or SW2, and/or SW3. In addition, PWGTDRV2 provides support to power gate peripheral loads on the SW4 supply domain. In typical applications, SW1, SW2, and SW3 will both be kept active for the processor modules in state retention, and SW4 retained for the external memory in self refresh mode. SW1, SW2, and SW3 power gating FET drive would typically be connected to PWGTDRV1 (for parallel NMOS switches). SW4 power gating FET drive would typically be connected to PWGTDRV2. When low power Off mode is activated, the power gate drive circuitry will be disabled, turning off the NMOS power gate switches to isolate the maintained supply domains from any peripheral loading.
GNDSWLED
Ground for boost converter for serial LED drive
LEDMD, LEDAD, AND LEDKP
LEDMD - Main display backlight LED driver output. LEDAD - Auxiliary display backlight LED driver output. LEDKP - Keypad lighting LED driver output. Independent programmable current sink channels. LED strings must be connected from SWLEDOUT (anodes) to these pins (cathodes). When parallel strings are ganged together on a driver channel, ballasting resistance is recommended to help balance the currents in each leg.
LEDR, LEDG AND LEDB
General purpose LED driver output Red, Green and Blue respectively. Each channel provides flexible LED intensity control. These pins can also be used as general purpose open drain outputs for logic signaling, or as generic PWM generator outputs.
SWITCHERS SW1IN, SW2IN, SW3IN AND SW4IN
Switchers 1, 2, 3, and 4 input. Connect these pins to BP to supply Switchers 1, 2, 3, and 4.
GNDLED E5
Ground for LED drivers
SW1FB, SW2FB, SW3FB AND SW4FB
Switchers 1, 2, 3, and 4 feedback. Switchers 1, 2, 3, and 4 output voltage sense respectively. Connect these pins to the farther point of each of their respective SWxOUT pin, in order to sense and maintain voltage stability.
IC CORE VCORE
Regulated supply output for the IC analog core circuitry. It is used to define the PUMS VIH level during initialization. The bandgap and the rest of the core circuitry are supplied from VCORE. Place a 2.2 F capacitor from this pin to GNDCORE.
SW1OUT
Switcher 1 output. Buck switcher for processor core(s).
GNDSW1
Ground for Switcher 1.
VCOREDIG
Regulated supply output for the IC digital core circuitry. No external DC loading is allowed on VCOREDIG. VCOREDIG is kept powered as long as there is a valid supply and/or coin cell. Place a 2.2 F capacitor from this pin to GNDCORE.
SW2OUT
Switcher 2 output. Buck switcher for processor SOG, etc.
GNDSW2
Ground for Switcher 2.
REFCORE
Main bandgap reference. All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at REFCORE. No external DC loading is allowed on REFCORE. Place a 100 nF capacitor from this pin to GNDCORE.
SW3OUT
Switcher 3 output. Buck switcher for internal processor memory and peripherals.
GNDSW3
Ground for switcher 3.
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Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
SW4OUT
Switcher 4 output. Buck switcher for external memory and peripherals.
or a 2.2V nominal external switched mode power supply rail, to improve power dissipation.
VPLL
Output of regulator for processor PLL. Quiet analog supply (PLL, GPS).
GNDSW4
Ground for switcher 4.
DVS1 AND DVS2
Switcher 1 and 2 DVS input pins. Provided for pin controlled DVS on the buck switchers targeted for processor core supplies. The DVS pins may be reconfigured for Switcher Increment / Decrement (SID) mode control. When transitioning from one voltage to another, the output voltage slope is controlled in steps of 25 mV per time step. These pins must be set high in order for the DVS feature to be enabled for each of switchers 1 or 2, or low to disable it.
VDIG
Output regulator Digital. Low voltage digital (DPLL, GPS).
VVIDEODRV
Drive output for VVIDEO external PNP transistor.
VVIDEO
Output regulator TV DAC. This pin must be connected to the collector of the external PNP transistor of the VVIDEO regulator.
SWBSTIN
Switcher BST input. The 2.2 H switcher BST inductor must be connected here.
VINAUDIO
Input regulator VAUDIO. Typically connected to BP.
SWBSTOUT
Power supply for gate driver for the internal power NMOS that charges SWBST inductor. It must be connected to BP.
VAUDIO
Output regulator for audio supply.
SWBSTFB
Switcher BST feedback. When SWBST is configured to supply the UVBUS pin in OTG mode the feedback will be switched to sense the UVBUS pin instead of the SWBSTFB pin.
VINUSB2
Input regulator VUSB2. This pin must always be connected to BP even if the regulators are not used by the application.
VUSB2
Output regulator for powering USB PHY.
GNDSWBST
Ground for switcher BST.
VINCAMDRV
1. Input regulator camera using internal PMOS FET. Typically connected to BP. 2. Drive output regulator for camera voltage using external PNP device. In this case, this pin must be connected to the base of the PNP in order to drive it.
REGULATORS VINIOHI
Input of VIOHI regulator. Connect this pin to BP in order to supply VIOHI regulator.
VIOHI
Output regulator for high voltage IO. Fixed 2.775 V output for high voltage level interface.
VCAM
Output regulator for the camera module. When using an external PNP device, this pin must be connected to its collector.
VINPLL AND VINDIG
The input of the regulator for processor PLL and Digital regulators respectively. VINDIG and VINPLL can be connected to either BP or a 1.8 V switched mode power supply rail, such as from SW4 for the two lower set points of each regulator (the 1.2 and 1.25 V output for VPLL, and 1.05 and 1.25 V output for VDIG). In addition, when the two upper set points are used (1.50 and 1.8V outputs for VPLL, and 1.65 and 1.8V for VDIG), they can be connected to either BP
VSDDRV
Drive output for the VSD external PNP transistor.
VSD
Output regulator for multi-media cards such as micro SD, RS-MMC.
VGEN1DRV
Drive output for the VGEN1 external PNP transistor.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
VGEN1
Output of general purpose 1 regulator.
GPO4
General purpose output 4. It can be configured for a muxed connection into Channel 7 of the GP ADC.
VGEN2DRV
Drive output for the VGEN2 external PNP transistor.
CONTROL LOGIC LICELL
Coin cell supply input and charger output. The LICELL pin provides a connection for a coin cell backup battery or supercap. If the main battery is deeply discharged, removed, or contact-bounced (i.e., during a power cut), the RTC system and coin cell maintained logic will switch over to the LICELL for backup power. This pin also works as a currentlimited voltage source for battery charging. A small capacitor should be placed from LICELL to ground under all circumstances.
VGEN2
Output of general purpose 2 regulator.
VINGEN3DRV
1. Input for the VGEN3 regulator when no external PNP transistor used. Typically connected to BP. 2. Drive output for VGEN3 in case an external PNP transistor is used on the application. In this case, this pin must be connected the base of the PNP transistor.
VGEN3
Output of general purpose 3 regulator.
XTAL1
32.768 kHz Oscillator crystal connection 1.
VSRTC
Output regulator for the SRTC module on the processor. The VSRTC regulator provides the CLK32KMCU output level (1.2 V). Additionally, it is used to bias the Low Power SRTC domain of the SRTC module integrated on certain FSL processors.
XTAL2
32.768 kHz Oscillator crystal connection 2.
GNDRTC
Ground for the RTC block.
GNDREG1
Ground for regulators 1.
CLK32K
32 kHz Clock output for peripherals. At system start-up, the 32 kHz clock is driven to CLK32K (provided as a peripheral clock reference), which is referenced to SPIVCC. The CLK32K is restricted to state machine activation in normal on mode.
GNDREG2
Ground for regulators 2.
GNDREG3
Ground for regulators 3.
CLK32KMCU
32 kHz Clock output for processor. At system start-up, the 32 kHz clock is driven to CLK32KMCU (intended as the CKIL input to the system processor) referenced to VSRTC. The driver is enabled by the start-up sequencer and the CLK32KMCU is programmable for Low Power Off mode control by the state machine.
GPO1
General purpose output 1. Intended to be used for battery thermistor biasing. In this case, connect a 10 K resistor from GPO1 to ADIN5, and one from ADIN5 to GND.
GPO2
General purpose output 2.
RESETB AND RESETBMCU
Reset output for peripherals and processor respectively. These depend on the Power Control Modes of operation (See Functional Device Operation on page 48). These are meant as reset for the processor, or peripherals in a power up condition, or to keep one in reset while the other is up and running.
GPO3
General purpose output 3.
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42
Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
WDI
Watchdog input. This pin must be high to stay in the On mode. The WDI IO supply voltage is referenced to SPIVCC (normally connected to SW4=1.8 V). SPIVCC must therefore remain enabled to allow for proper WDI detection. If WDI goes low, the system will transition to the Off state or Cold Start (depending on the configuration).
STANDBY AND STANDBYSEC
Standby input signal from processor and from peripherals respectively. Table 8. Standby Control Pins
STANDBY (PIN) 0 x 1 x 0 0 1 1 STANDBYINV (SPI BIT) 0 x 1 x 1 1 0 0
To ensure that shared resources are properly powered when required, the system will only be allowed into Standby when both the application processor (which typically controls the STANDBY pin) and peripherals (which typically control the STANDBYSEC pin) allow it. This is referred to as a Standby event. The Standby pins are programmable for Active High or Active Low polarity, and that decoding of a Standby event will take into account the programmed input polarities associated with each pin. Since the Standby pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the pin level changes.
STANDBYSEC (PIN) x 0 x 1 0 1 0 1
STANDBYSECINV (SPI BIT) x 0 x 1 1 0 1 0
STANDBY CONTROL(42) 0 0 0 0 1 1 1 1
Notes 42. STANDBY = 0: System is not in Standby; STANDBY=1: System is in Standby and Standby programmability is activated.
The state of the Standby pins only have influence in the On mode and are therefore ignored during start up and in the Watchdog phase. This allows the system to power up without concern of the required Standby polarities, since software can make adjustments accordingly, as soon as it is running.
PUMS1 AND PUMS2
Power up mode supply setting. Default start-up of the device is selectable by hardwiring the Power Up Mode Select pins. The Power Up Mode Select pins (PUMS1 and PUMS2) are used to configure the start-up characteristics of the regulators. Supply enabling and output level options are selected by hardworking the PUMS pins for the desired configuration. The following power up defaults table shows the initial setup for the voltage level of the switchers and regulators, and if they get enabled or not, according to the PUMS pins configuration.
INT
Interrupt to processor. Unmasked interrupt events are signaled to the processor by driving the INT pin high.
PWRON1, 2 AND 3
A turn on event can be accomplished by connecting an open drain NMOS driver to the PWRONx pin of the 13892, so that it is in effect a parallel path for the power key.
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
Table 9. Power Up Defaults
i.MX PUMS1 PUMS2 SW1
(43)
37/51 GND OPEN 0.775 1.025 1.200 1.800 Off 3.300(44) 2.600 1.800 1.250 2.775 3.150 Off
37/51 OPEN OPEN 1.050 1.225 1.200 1.800 Off 3.300(44) 2.600 1.800 1.250 2.775 Off Off
37/51 VCOREDIG OPEN 1.050 1.225 1.200 1.800 Off 3.300(44) 2.600 1.800 1.250 2.775 3.150 Off
37/51 VCORE OPEN 0.775 1.025 1.200 1.800 Off 3.300(44) 2.600 1.800 1.250 2.775 Off Off
35 GND GND 1.200 1.350 1.800 1.800 5.000 3.300(46) 2.600 1.500 1.250 2.775 3.150 3.15
27/31 OPEN GND 1.200 1.450 1.800 1.800 5.000 3.300(46) 2.600 1.500 1.250 2.775 3.150 3.15
SW2(43) SW3(43) SW4
(43)
SWBST VUSB VUSB2 VPLL VDIG VIOHI VGEN2 VSD
Notes 43. The switchers SWx are activated in PWM pulse skipping mode allowed when enabled by the startup sequencer. 44. USB supplies VUSB, is only enabled if 5.0 V is present on UVBUS. 45. The following supplies are not included in the matrix, since they are not intended for activation by the start-up sequencer: VCAM, VGEN1, VGEN3, VVIDEO, and VAUDIO. 46. SWBST = 5.0 V, powers up, as does VUSB, regardless of the 5.0 V present on UVBUS. By default VUSB will be supplied by SWBST.
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Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
Table 10. Power Up Sequence
Tap x 2.0 ms 0 1 2 3 4 5 6 7 8 9 VUSB(49), VUSB2 PUMS2 = OPEN (I,MX37,i.MX51) SW2 SW4 VIOHI VGEN2 SW1 SW3 VPLL VDIG PUMS2 = GND (i.MX35,i.MX27) SW2 VGEN2 SW4 VIOHI, VSD SWBST, VUSB(50) SW1 VPLL SW3 VDIG VUSB2
Notes 47. Time slots may be included for blocks which are defined by the PUMS pins as disabled, to allow for potential activation. 48. The following supplies are not included in the matrix, since they are not intended for activation by the start-up sequencer: VCAM, VGEN1, VGEN3, VVIDEO, and VAUDIO. SWBST is not included on the PUMS2 = Open column 49. USB supplies VUSB, is only enabled if 5.0 V is present on UVBUS. 50. SWBST = 5.0 V, powers up, as does VUSB, regardless of the 5.0 V present on UVBUS. By default VUSB will be supplied by SWBST.
MODE
USB LBP mode, normal mode, test mode selection & antifuse bias. During evaluation and testing, the IC can be
MODE PIN STATE Ground VCOREDIG VCORE MODE Normal Operation
configured for normal operation or test mode via the MODE pin as summarized in the following table.
USB Low Power Boot Allowed Test Mode
GNDCTRL
Ground for control logic.
CLK
Primary SPI clock input. In I2C mode, this pin is the SCL signal (I2C bus clock).
SPIVCC
Supply for SPI bus and audio bus
MOSI
Primary SPI write input. In I2C mode, the MOSI pin hard wired to ground or VCORE is used to select between two possible addresses (A0 address selection).
CS
CS held low at Cold Start configures the interface for SPI mode. Once activated, CS functions as the SPI Chip Select. CS tied to VCORE at Cold Start configures the interface for I2C mode; the pin is not used in I2C mode other than for configuration. Because the SPI interface pins can be reconfigured for reuse as an I2C interface, a configuration protocol mandates that the CS pin is held low during a turn on event for the IC (a weak pull-down is integrated on the CS pin).
MISO
Primary SPI read output. In I2C mode, this pin is the SDA signal (bi-directional serial data line).
GNDSPI
Ground for SPI interface.
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
USB UID
This pin identifies if a mini-A or mini-B style plug has been connected to the application. The state of the ID detection Table 11. UID Pin Levels
UID PIN EXTERNAL CONNECTION Resistor to Ground Grounded Floating Voltage Applied Notes 51. UID maximum voltage is 5.25 V
can be read via the SPI, to poll dedicated sense bits for a floating, grounded, or factory mode condition on the UID pin.
UID PIN VOLTAGE 0.18*VCOREACCESSORY Non-USB accessory is attached A type plug (USB Host) B type plug (USB peripheral, OTG device or no device) is attached Factory mode
UVBUS
1. USB transceiver cable interface. 2. OTG supply output. When SWBST is configured to supply the UVBUS pin in OTG mode, the feedback will switch to sense the UVBUS pin instead of the SWBSTFB pin.
thermistor must be biased with an external pull-up to a voltage rail greater than the ADC input range. In order to save current when the thermistor reading is not required, it can be biased from one of the general purpose IOs such as GPO1. A resistor divider network should assure the resulting voltage falls within the ADC input range, in particular when the thermistor check function is used.
VUSB
This is the regulator used to provide a voltage to an external USB transceiver IC.
ADIN6
ADC generic input channel 6. ADIN6 may be used as a general purpose unscaled input, but in a typical application, the PA thermistor is connected here.
VINUSB
Input option for VUSB; supplied by SWBST. This pin is internally connected to the UVBUS pin for OTG mode operation (for more details about OTG mode See OTG mode (On the Go) on page 64). Note: When VUSBIN =1 , UVBUS will be connected via internal switches to VINUSB and incur some current drain on that pin, as much as 270uA maximum, so care must be taken to disable this path and set this SPI bit (VUSBIN) to 0 to minimize current drain, even if SWBST and/or VUSB are disabled.
ADIN7
ADC generic input channel 7, group 1. ADIN7 may be used as a general purpose unscaled input or as a divide by 2 scaled input. In a typical application, an ambient light sensor is connected here. A second general purpose input ADIN7B is available on channel 7. This input is muxed on the GPO4 pin. In the application, a second ambient light sensor is supposed to be connected here.
VBUSEN
External VBUS enable pin for the OTG supply. VBUS is defined as the power rail of the USB cable (+5.0 V).
TSX1 AND TSX2, TSY1 AND TSY2
Note: The TS[xy] [12] inputs must not exceed BP or VCORE. Touch Screen Interfaces X1 and X2, Y1 and Y2. The touch screen X plate is connected to TSX1 and TSX2, while the Y plate is connected to Y1 and Y2. In inactive mode, these pins can also be used as general purpose ADC inputs. They are respectively mapped on ADC channels 4, 5, 6, and 7. In interrupt mode, a voltage is applied to the X-plate (TSX2) via a weak current source to VCORE, while the Yplate is connected to ground (TSY1).
A TO D CONVERTER
Note: The ADIN5/6/7 inputs must not exceed BP.
ADIN5
ADC generic input channel 5. ADIN5 may be used as a general purpose unscaled input, but in a typical application, ADIN5 is used to read out the battery pack thermistor. The
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Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
TSREF
Touch Screen Reference regulator. This regulator is powered from VCORE. In applications not supporting touch screen, the TSREF can be used as a low current general purpose regulator, or it can be kept disabled and the bypass capacitor omitted.
GNDADC
Ground for A to D circuitry.
THERMAL GROUNDS GNDSUB1-9
Non critical signal grounds and thermal heat sinks.
ADTRIG
ADC trigger input. A rising edge on this pin will start an ADC conversion.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION
FUNCTIONAL DEVICE OPERATION PROCESSOR LOGIC INTERFACING
CLOCK GENERATION
A system clock is generated for internal digital circuitry as well as for external applications utilizing the clock output pins. A crystal oscillator is used for the 32.768 kHz time base and generation of related derivative clocks. If the crystal oscillator is not running (for example, if the crystal is not present), an internal 32 kHz oscillator will be used instead. Support is also provided for an external Secure Real Time Clock (SRTC), which may be integrated on a companion system processor IC. For media protection in compliance with Digital Rights Management (DRM) system requirements, the CLK32KMCU can be provided as a reference to the SRTC module, where tamper protection is implemented. The internal 32kHz oscillator is an integrated backup for the crystal oscillator and provides a 32.768 kHz nominal frequency at 20% accuracy if running. The internal oscillator only runs if a valid supply is available at BP and would not be used as long as the crystal oscillator is active. In absence of a valid supply at the BP supply node (for instance due to a dead battery), the crystal oscillator continues running supplied from the coin cell battery until the coin cell is depleted. All control functions will run off the crystal derived frequency, occasionally referred to as "32 kHz" for brevity's sake. The crystal oscillator has been optimized for use in conjunction with the Micro Crystal CC7V-T1A32.768 kHz-9.0 pF-30 ppm or equivalent (such as the Micro Crystal CC5V-T1A or Epson FC135) is capable of handling its parametric variations. The electrical characteristics of the 32 kHz crystal oscillator are given in Tables 4 and 6, taking into account the crystal characteristics noted previously. The oscillator accuracy depends largely on the temperature characteristics of the used crystal. Application circuits can be optimized for required accuracy by adapting the external crystal oscillator network (via component accuracy and/or tuning). Additionally, a clock calibration system is provided to adjust the 32,768 cycle counter that generates the 1.0 Hz timer and RTC registers; see the RTC section for more detail. by connecting an open drain NMOS driver to the PWRON pin of 13892 so that it is in effect a parallel path for the power key. The 13892 will not be able to discern the turn on event from a normal power key initiated turn on, but the processor should have the knowledge since the RTC initiated turn on is generated locally. The VSRTC regulator provides the CLK32KMCU output level. It is also used to bias the Low Power SRTC domain of the SRTC module integrated on certain FSL processors. The VSRTC regulator is enabled as soon as the RTCPORB is detected. The VSRTC cannot be disabled.
VSRTC
REAL TIME CLOCK
A Real Time Clock (RTC) is provided with time and day counters as well as an alarm function. The RTC utilizes the 32.768 kHz crystal oscillator for the time base, and is powered by the coin cell backup supply when BP has dropped below operational range. In configurations where the SRTC is used, the RTC can be disabled to conserve current drain by setting the RTCDIS bit to a 1 (defaults on at power up).
TIME AND DAY COUNTERS
The 32.768 kHz clock is divided down to a 1.0 Hz time tick which drives a 17 bit Time Of Day (TOD) counter. The TOD counter counts the seconds during a 24 hour period from 0 to 86,399 and will then roll over to 0. When the roll over occurs, it increments the 15 bit DAY counter. The DAY counter can count up to 32767 days. The 1.0 Hz time tick can be used to generate a 1.0 Hz interrupt if unmasked.
TIME OF DAY ALARM
A Time Of Day Alarm (TODA) function can be used to turn on the application and alert the processor. If the application is already on, the processor will be interrupted. The TODA and DAYA registers are used to set the alarm time. When the TOD counter is equal to the value in TODA and the DAY counter is equal to the value in DAYA, the TODAI interrupt will be generated.
TIMER RESET SRTC SUPPORT AND VSRTC
When configured for DRM mode (SPI bit DRM=1), the CLK32KMCU driver will be kept enabled through all operational states to ensure that the SRTC module always has its reference clock. If DRM=0, the CLK32KMCU driver will not be maintained in the Off state. It is also necessary to provide a means for the processor to do an RTC initiated wake-up of the system if it has been programmed for such capability. This can be accomplished
13892
As long as the supply at BP is valid, the real time clock will be supplied from VCORE. If not, it can be backed up from a coin cell via the LICELL pin. When the backup voltage drops below RTCUVDET, the RTCPORB reset signal is generated and the contents of the RTC will be reset. Additional registers backed up by coin cell will also reset with RTCPORB. To inform the processor that the contents of the RTC are no longer valid due to the reset, a timer reset interrupt function is implemented with the RTCRSTI bit.
48
Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION
COIN CELL BATTERY BACKUP
The LICELL pin provides a connection for a coin cell backup battery or supercap. If the main battery is deeply discharged, removed, or contact-bounced (i.e., during a power cut), the RTC system and coin cell maintained logic will switch over to the LICELL for backup power. A small capacitor should be placed from LICELL to ground under all circumstances. Coin cells can get damaged and their lifetime reduced when deeply discharged. In order to avoid this, the internal circuitry supplied from LICELL is disconnected for voltages Table 12. 13892 Coin Cell Battery Electrical Characteristics
PARAMETER Voltage Accuracy Coin Cell Charge Current in On and Watchdog modes ICOINHI
below the coin cell disconnect threshold. This will also cause the ADC reading of the coin cell voltage to yield zero. The coin cell charger circuit will function as a currentlimited voltage source, resulting in the CC/CV taper characteristic typically used for rechargeable Lithium-Ion batteries. The coin cell voltage is programmable from 2.5 to 3.3 V in 0.1 V steps, excepting 2.6 V. The coin cell charger voltage is programmable in the ON state where the charge current is fixed at ICOINHI. When the device is working in any of the low Power Off modes, the coin cell charger will also go into a low power mode in which the current it supplies to the coin cell will be reduced in order to save power.
TYP 100 60 10 30 100 4.7
UNITS mV A A % nF F
Coin Cell Charge Current in Off and Low Power Off modes (User Off/Memory Hold) ICOINLO Current Accuracy LICELL Bypass Capacitor LICELL Bypass Capacitor as coin cell
CONTROL INTERFACE SPI/I2C
The IC contains a number of programmable registers for control and communication. The majority of registers are accessed through an SPI interface in a typical application.
The same register set may be alternatively accessed with an I2C interface that is muxed on SPI pins. The following table describes the muxed pin options for the SPI and I2C interfaces.
Table 13. 13892 Muxed Pin Options for SPI and I2C Interfaces (SPI Functions)
PIN NAME CS SPI MODE FUNCTIONALITY Configuration (52) Chip Select CLK MISO MOSI SPI Clock Master In, Slave Out (data input) Master Out, Slave In (data input)
Notes 52. CS held low at Cold Start configures the interface for SPI mode; once activated, CS functions as the SPI Chip Select.
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION
SPI INTERFACE
The IC contains a SPI interface port which allows access by a processor to the register set. Via these registers, the resources of the IC can be controlled. The registers also provide status information about how the IC is operating as well as information on external signals. The SPI port utilizes 32-bit serial data words comprised of 1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits. The addressable register map spans 64 registers of 24 data bits each.
I2C INTERFACE
When configured for I2C mode, the interface may be used to access the complete register map. Since SPI configuration is more typical, references within this document will generally refer to the common register set as a "SPI map" and bits as "SPI bits". However, it should be understood that access reverts to I2C mode when configured as such. The SPI pins CLK and MISO are reused for the SCL and SDA lines respectively. Selection of I2C mode for the interface is configured by hardwiring the CS pin to VCORE on the application board.
Table 14. Muxed Pin Options for SPI and I2C Interfaces (I2C Functions)
PIN NAME CS CLK MISO MOSI Notes 53. 54. CS tied to VCORE at Cold Start configures interface for I2C mode; the pin is not used in I2C mode other than for configuration. In I2C mode, the MOSI pin hard wired to ground or VCORE is used to select between two possible addresses.
I2C Mode Functionality
Configuration(53) SCL: I2CBUS clock SDA: Bi-directional serial data line A0 Address Selection(54)
The I2C mode of the interface is implemented generally following the Fast Mode definition, which supports up to 400 kbits/s operation. (exceptions to the standard are noted to be 7-bit only addressing and no support for General Call addressing). Timing diagrams, electrical specifications, and further details can be found in the I2C specification, which is available for download at: http://www.nxp.com/acrobat_download/literature/9398/ 39340011.pdf
INTERRUPT CONTROL
The system is informed about important events based on interrupts. Unmasked interrupt events are signaled to the processor by driving the INT pin high; this is true whether the communication interface is configured for SPI or I2C. Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each interrupt can be cleared by writing a 1 to the appropriate bit in the Interrupt Status register. This will also cause the interrupt line to go low. If a new interrupt occurs while the
processor clears an existing interrupt bit, the interrupt line will remain high. Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high, the interrupt line will not go high. A masked interrupt can still be read from the Interrupt Status register. This gives the processor the option of polling for status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the device to determine if any interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked interrupt bit was already high, the interrupt line will go high after unmasking. Interrupts generated by external events are debounced; therefore, the event needs to be stable throughout the debounce period before an interrupt is generated. Nominal debounce periods for each event are documented in the INT summary table following later in this chapter. Due to the asynchronous nature of the debounce timer the effective debounce time can vary slightly.
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION
SUPPLIES
A system power scheme for portable devices is provided which includes both switching and linear regulators. Various operational modes are available for the power circuitry, which may be accessible through SPI programming and the state of the STANDBY pins. Programmable Standby mode configuration allows automated system level control to optimize quiescent efficiency without the need for or latency of SPI intervention.
The switch mode supply subsystem include a core block for clock generation, 4 step down (buck) switching regulators and two step up (boost) switching regulators. Linear regulators are provided for key power domains not supplied directly by switching regulators or the battery. Pass devices are integrated for most regulators for board area and cost advantages. External PNP pass devices are used selectively to help manage internal power dissipation. A general application of the power tree is illustrated in the Figure 6 diagram. Supply names are suggestive of typical applications, but not restrictive.
Figure 6. General Application of the Power Tree The minimum operating voltage for the supply tree while devices and interfaces, which can run at the same voltage maintaining the performance as specified is 3.0 V. For lower level. SW4 is used for powering external memory as well as voltages, the performance may be degraded. low voltage peripheral devices and interfaces, which can run at the same voltage level. An anticipated platform use case applies SW1 and SW2 to BUCK CONVERTERS processor power domains that require voltage alignment to Four buck switchers are provided with integrated power allow direct interfacing without bandwidth limiting switches and synchronous rectification. In a typical synchronizers. application, SW1 and SW2 are used for supplying the The buck switchers are supplied from the system supply Application Processor core power domains. Split power BP, which is drawn from the main battery or the battery domains allow independent DVS control for processor power charger (when present). Figure 7 shows a high level block optimization, or to support technologies with a mix of device diagram of the buck switchers. types with different voltage ratings. SW3 is used for powering internal processor memory as well as low voltage peripheral
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION
Figure 7. Buck Switch Diagram The Buck switcher topology includes an integrated (DVS) by using SPI driven voltage steps, state machine synchronous rectifier, meaning that the rectifying diode is defined modes, and direct DVSx pin control. SW1 and SW2 implemented on chip as a low ohmic FET. The placement of also include the Switcher Increment/Decrement (SID) an external diode is therefore not required, but overall feature, with which, an increment command will increase the switcher efficiency may benefit from this. The buck set point voltage by a single 25 mV step, and a decrement command will decrease it in the same amount of voltage. The converters permit a 100% duty cycle operation. transition time for the step will be the same as programmed During normal operation several power modes are for the DVS feature. Maximum and minimum voltages are possible, depending on the loading. For medium and full programmable to ensure the switcher voltage does not go out loading, synchronous PWM control is the most efficient while a specific range. Panic mode is also included to quickly return maintaining a constant switching frequency. the switcher voltage to its normal programmed set point. The output voltages of the buck switchers are SPI When initially activated, switcher outputs will apply configurable and two output ranges are available, individually controlled stepping to the programmed value. The soft start programmed with SWxHI for SW2, SW3, and SW4 bucks, feature limits the inrush current at startup. SW1 is limited to only one output range. Presets are available Point of Load feedback is intended for minimizing errors for both the Normal and Standby operation. due to board level IR drops. The first voltage range that applies for all the Buck switchers goes from 0.6 to 1.375 V in 25 mV steps. The MODES OF OPERATION second one does not apply for SW1 and goes from 1.1 to 1.85 V also in 25 mV steps. Two PWM modes are available: SW1 and SW2 include pin controlled Dynamic Voltage PWM-NPS: sacrifices low load efficiency for a continuous Scaling (DVS) operation. When transitioning from one switching operation. voltage to another, the output voltage slope is controlled in PWM-PS: offers better low load efficiency by allowing the steps of 25 mV per time step (time step as defined for DVS absence of switching cycles at low output loading. This pulse stepping for SW1 and SW2, fixed at 4.0 s for SW3, and SW4). This allows for support of dynamic voltage scaling
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Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION
skipping feature improves efficiency by reducing dynamic switching losses simply by switching less often. In its lowest power mode, the switcher can regulate using hysteresis control known as a Pulse Frequency Modulation (PFM) control scheme. The frequency spectrum will be a function of input and output voltage, loading, and the external components. Due to its spectral variance and lighter drive capability, PFM mode is generally reserved for non-active radio modes and Deep Sleep operation.
environment, the PLL can be programmed via SPI from a multiplication factor of 84 to 105, in steps of 3.
BOOST CONVERTERS
SWBST
SWBST is a boost switching regulator with a fixed 5.0 V output. It runs at 2/3 of the switcher PLL frequency. SWBST supplies the VUSB regulator for the USB system in OTG mode, as well as the VBUS voltage at the UVBUS pin. When SWBST is configured to supply the UVBUS pin in OTG mode, the feedback will be switched to sense the UVBUS pin instead of the SWBSTFB pin. Therefore, when driving the VBUS for OTG mode, the output of the switcher may rise to 5.75 V to compensate for the voltage drops in the internal switches. Note that the parasitic leakage path for a boost switcher will cause the output voltage SWBSTOUT and SWBSTFB to sit at a Schottky drop below the battery voltage, whenever SWBST is disabled. The switching NMOS transistor is integrated on-chip. An external fly back Schottky diode, inductor, and capacitor are required.
CURRENT LIMITER
A built in current limiter ensures that during normal operation the maximum current through the coil is not exceeded (refer to Electrical Characteristics). This current limiter can be disabled by SPI bits.
SWITCHING FREQUENCY
A PLL generates the switcher system clocking from the 32.768 kHz crystal oscillator reference. To allow for spectral optimization for reduction of spurious influence in a radion
Figure 8. 13892 SWBST Block Diagram.
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION
Main characteristics of SWBST are summarized in Tables 4 and 6.
SWLED
The supply to the serial LEDs is provided by an inductive boost switcher as illustrated in Figure 9. The boost converter is automatically enabled when one or more backlight drivers are enabled.
sense resistor which creates a drop that is then compared to a fixed voltage. The output of the comparator is the flag of over-current in the output driver of the boost converter. When an over-current is detected, the PWM cycle is stopped by turning off the internal NMOS, which allows the current in the coil to decrease. Over-voltage Protection The boost converter contains a two phase over-voltage detection to prevent the SWLEDOUT from rising higher than 28V.
LDOS
The following is a description of the linear regulators. For convenience these regulators are named to indicate their typical or possible applications, but the supplies are not limited to these uses, and may be applied to any loads within the specified regulator capabilities. A low power standby mode controlled by STANDBY is provided in which the bias current is aggressively reduced. This mode is useful for deep sleep operations, where certain supplies cannot be disabled, but active regulation can be tolerated with lesser parametric requirements. The output drive capability and performance are limited in this mode. Apart from the integrated linear regulators, there are also GPO output pins provided to enable and disable discrete regulators or functional blocks, or to use as general purpose outputs for any system need. For example, one application may be to enable a battery pack thermistor bias in synchronization with timed ADC conversions. All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at REFCORE. The bandgap and the rest of the core circuitry is supplied from VCORE. The performance of the regulators is directly dependent on the performance of VCOREDIG and the bandgap. No external DC loading is allowed on VCOREDIG or REFCORE. VCOREDIG is kept powered as long as there is a valid supply and/or coin cell. The following table captures the main characteristics of the core circuitry.
Figure 9. The boost converter output voltage is adapted automatically to the load such that the headroom on the active LED drivers is maintained at a sufficient level (output voltage range from BP to 25.5 V). This allows for a very efficient backlighting scheme. The control is time continuous. When accounting for the diode drop and the driver headroom, the total available supply for the LEDs will be sufficient for up to 6 white LEDs in series. The boost converter runs at 2/3 of the switcher PLL generated frequency.
PROTECTION FUNCTIONS
Current Limit SWBST has an over-current limit protection of 1.5 A. A portion of the output current is sensed across an internal
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Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION
Table 15. Core Circuitry Main Characteristics
REFERENCE PARAMETER Output voltage in ON mode VCOREDIG (Digital core supply) Output voltage in OFF Bypass Capacitor Output voltage in ON mode VCORE (Analog core supply) Output voltage in OFF Bypass Capacitor REFCORE (Bandgap/Regulator Reference) Output voltage(55)
(55), (56) (55), (56)
TYPICAL 1.5 V 1.2 V 2.2 F typ (0.65 F derated) 2.775 V 0V 2.2 F typ (0.65 F derated) 1.20 V 100 nF typ (65 nF derated)
mode(56)
mode(56)
Bypass Capacitor
Notes 55. 3.0 V < BP < 4.65 V, no external loading on VCOREDIG, VCORE, or REFCORE. Extended operation down to UVDET with VCORE down to UVDET, but no system malfunction. 56. The core is in On mode when charging, or when the state machine of the IC is not in the Off mode, nor in the power cut mode. Otherwise, the core is in Off mode.
The transient load and line response are specified with the waveforms as depicted in Figure 10. Note that where the transient load response refers to the overshoot only, so
excluding the DC shift itself, the transient line response refers to the sum of both overshoot and DC shift. This is also valid for the mode transition response.
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Figure 10. Transient Response Waveforms
VAUDIO AND VVIDEO SUPPLIES
The primary applications of these power supplies are for audio, and TV-DAC. These supplies could also be used for other peripherals if one of these functions is not required. Low Power modes and programmable Standby options can be used to optimize power efficiency during deep sleep modes. VAUDIO is implemented with an integrated PMOS pass FET and has a dedicated input supply pin VINAUDIO. The nominal output voltage (VNOM as referred in Table Table 4) of VVIDEO can go from 2.5 to 2.7 V on 0.1 V steps, it also can be programmed to be 2.775 V. Its output current depends on the external pass device. The nominal output voltage (VNOM as referred in Table Table 4) of VAUDIO can be programmed to be 2.3, 2.5, 2.775 or 3.0 V.
LOW VOLTAGE SUPPLIES
VDIG and VPLL are provided for isolated biasing of the Baseband system PLLs for clock generation in support of
protocol and peripheral needs. Depending on the lineup and power requirements, these supplies may be considered for sharing with other loads, but noise injection must be avoided and filtering added if necessary, to ensure suitable PLL performance. The VDIG and VPLL regulators have a dedicated input supply pin: VINDIG for the VDIG regulator and VINPLL for the VPLL regulator. VINDIG and VINPLL can be connected to either BP or a 1.8 V switched mode power supply rail such as from SW4 for the two lower set points of each regulator (1.2 V and 1.25 V output for VPLL and 1.05 and 1.25 V output for VDIG). In addition, when the two upper set points are used (1.50 V and 1.8 V output for VPLL and 1.65 V and 1.8 V for VDIG) can be connected to either BP or a 2.2 V nominal external switched mode power supply rail to improve power dissipation. The nominal programmable output voltage of VPLL (VNOM as referred in Table 4) could be 1.2, 1.25, 1.50 or 1.8 V, while VDIG can be configured to 1.05, 1.25, 1.65 and 1.8 V.
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Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION
PERIPHERAL INTERFACING
IC interfaces in the lineups generally fall in two categories: low voltage IO primarily associated with the AP IC and certain peripherals at the SPIVCC level (powered from SW4), and a higher voltage interface level associated with other peripherals not compatible with the 1.8 V SPIVCC. VIOHI is provided at a fixed nominal output voltage 2.775 V level (VNOM as referred in Table 4) for such interfaces, and may also be applied to other system needs within the guidelines of the regulator specifications. The input VINIOHI is not only used by the VIOHI regulator, but also by other blocks. Therefore it should always be connected to BP, even if the VIOHI regulator is not used by the system. VIOHI has an internal PMOS pass FET which will support loads up to 100 mA.
USB SUPPLY
The VUSB regulator is used to supply a nominal output voltage (VNOM as referred in Table 4) of 3.3 V to the external USB PHY. The UVBUS line of the USB interface is supplied by the host, in the case of host mode operation, or by the integrated VBUS generation circuit, in the case of USB OTG mode operation. The VBUS circuit is powered from the SWBST boost supply, to ensure OTG current sourcing compliance through the normal discharge range of the main battery. The VUSB regulator can be supplied from the VBUS wire of the USB cable (power rail of the USB cable), when supplied by a host, in the case of host mode operation, or by the SWBST voltage for OTG mode operation. The SWBST voltage supplies the VUSB regulator from the VINUSB pin, which is internally connected to SWBST, and also to the UVBUS pin to drive the VBUS on this mode (as long as VBUSEN pin is logic high =1). When UVBUS/CHARGRAW is detected in host mode, the USB regulators, VUSB and VUSB2 should be automatically enabled. It will be up to the processor to determine what type of device is connected, either a USB host or a wall charger, and take appropriate action. The VUSB and VUSB2 regulators can be enabled independent of OTG or Host Mode by setting the individual SPI enable bits, VUSBEN and VUSB2EN respectively. Since UVBUS can be shared with the charger input at the board level, the UVBUS node must be able to withstand the same high voltages as the charger. In over-voltage conditions, the VUSB regulator is disabled. USB supplies characteristics are shown in Tables 4 and 6. Note: When VUSBIN =1 , UVBUS will be connected via internal switches to VINUSB and incur some current drain on that pin, as much as 270 A maximum, so care must be taken to disable this path and set this SPI bit (VUSBIN) to 0 to minimize current drain, even if SWBST and/or VUSB are disabled.
CAMERA
The camera module is supplied by the regulator VCAM. This allows for powering the entire module independent of the rest of other parts of the system, as well as to select from a number of VCAM output levels for camera vendor flexibility. In applications with a dual camera, it is anticipated that only one of the two cameras is active at a time, allowing the VCAM supply to be shared between them. VCAM has an internal PMOS pass FET, which will support up to 2Mpixel Camera modules (<65 mA). To support higher resolution cameras, an external PNP is provided. The external PNP configuration is offered to avoid excess on-chip power dissipation at high loads and large differential between BP and output settings. For lower current requirements, an integrated PMOS pass FET is included. The input pin for the integrated PMOS option is shared with the base current drive pin for the PNP option. The nominal output voltage of this regulator (VNOM as referred in Table 4) is SPI configurable, and can be 2.5, 2.6, 2.75, or 3.0 V. The output current when working with the internal pass FET is 65 mA, and could be up to 250 mA when working with an external PNP.
MULTI-MEDIA CARD SUPPLY
This supply domain is generally intended for user accessible multi-media cards such as Micro-SD (TransFlash), RS-MMC, and the like. An external PNP is utilized for this LDO to avoid excess on-chip power dissipation at high loads and large differential between BP and output settings. The external PNP device is always connected to the BP line in the application. VSD may also be applied to other system needs within the guidelines of the regulator specifications. At the 1.8 V set point, the VSD regulator can be powered from and external buck switcher (2.2 V typ) for an efficiency advantage and reduced power dissipation in the pass devices. This regulator can be configured for nominal output voltages (VNOM as referred in Table 4) of 1.8, 2.00, 2.60, 2.70, 2.8, 2.9, 3.00, and 3.15 V. All of these configurations can draw a current of 250 mA.
VUSB REGULATOR
VUSB2 is implemented with an integrated PMOS pass FET and has a dedicated supply pin VINUSB2. The pin VINUSB2 should always be connected to BP, even in case the regulators are not used by the application. The nominal output voltage of this regulator (VNOM as referred in Table 4) can be programmed to be 2.400, 2.600, 2.700, and 2.775 V with a load capability of 50 mA.
GEN1, GEN2 AND GEN3 REGULATORS
General purpose LDOs VGEN1, VGEN2, and VGEN3 are provided for expansion of the power tree, to support peripheral devices which could include WLAN, BT, GPS, or other functional modules. All the regulators include programmable set points for system flexibility. At the 1.2 V and 1.5 V set points, both VGEN1 and VGEN2 can be powered from an external buck switcher (2.2 V typ), for an
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION
efficiency advantage and reduced power dissipation in the pass devices. VGEN1 nominal output voltage (VNOM as referred in Table 4) can be 1.20, 1.50, 2.7775, or 3.15 V, and has a capability of 200 mA. VGEN2 is configurable for 1.20, 1.50, 1.60, 1.80, 2.70, 2.80, 3.00, and 3.15 V, and can supply up to 350 mA. VGEN3 has an internal PMOS pass FET, which will support loads up to 50 mA. For higher current capability, drive for an external PNP is provided. The external PNP configuration is offered to avoid excess on-chip power dissipation at high loads and large differential between BP and output settings. The input pin for the integrated PMOS option is shared with the base current drive pin for the PNP option. This regulator is configurable for nominal output voltages (VNOM as referred in Table 4) of 1.80 and 2.90 V with a capability of 200 mA when working with an external PNP.
GENERAL PURPOSE OUTPUTS
The GPO drivers included can provide useful system level signaling with SPI enabling and programmable Standby
control. Key use cases for GPO outputs include battery pack thermistor biasing and enabling of peripheral devices, such as light sensor(s), camera flash, or even supplemental regulators. SPI enabling can be used for coordinating GPOs with ADC conversions for consumption efficiency and desired settling characteristics. The GPO1 output is intended to be used for battery thermistor biasing. For accurate thermistor reading by the ADC, the output resistance of the GPO1 driver is of importance. Finally, a muxing option is included to allow GPO4 to be configured for a muxed connection into Channel 7 of the GP ADC. As an example for a dual light sensor application, Channel 7 can be toggled between the ADIN7 (ADINSEL7=00) and GPO4 (ADINSEL7=11), for convenient connectivity and monitoring of two sensors. The GPO4 pin is configured for ADC input mode by default (GPO4ADIN=1), so that the GPO driver stage is at high impedance at power up. The GPO4 pin can be configured by software for GPO operation with GPO4ADIN=0.
Table 16. 13892 General Purpose Outputs Electrical Characteristics
PIN NAME GPO1 PARAMETER Output Low Output High Output Low Output High LOAD CONDITION -400 A 400 A -100 A 100 A MIN 0 VCORE-0.2 0 VIOHI-0.2 MAX 0.2 VCORE 0.2 VIOHI UNIT V V V V
GPO2, GPO3, GPO4
PROTECTION FUNCTIONS
SHORT-CIRCUIT PROTECTION
The higher current LDOs, and those most accessible in product applications, include short-circuit detection and protection (VVIDEO, VAUDIO, VCAM, VSD, VGEN1, VGEN2, and VGEN3). The short-circuit protection (SCP) system includes debounced fault condition detection, regulator shutdown, and processor interrupt generation to contain failures and minimize chance of product damage. If a short-circuit condition is detected, the LDO will be disabled by resetting its VxEN bit while at the same time an interrupt SCPI will be generated to flag the fault to the system processor.
BATTERY MANAGEMENT
The 13892 supports single path and serial path charging. In single path charging, the device is always supplied from the battery and therefore always has to be present and valid.
In a serial path charging scheme, the device may operate directly from the charger while the battery is removed or deeply discharged. The charger supports charging from a USB host or a wall charger. The charger interface provides linear operation via an integrated DAC at programmable current levels. It incorporates a standalone trickle charge mode, in case of a dead battery with dual LED indicator driver. Over-voltage, short-circuit, and under-voltage detectors are included as well as charger detection and removal. The charger includes the necessary circuitry to allow for USB charging and for reverse supply to an external accessory. The battery management system also provides a battery presence detector, and an A to D converter that serves for measuring the charge current, battery and other supply voltages, as well as for measuring the battery thermistor and die temperature. Finally, a system is included for monitoring the current drawn from, or charged into the main battery for support of a Coulomb Counter function.
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION
Figure 11. 13892 Charge Path Transistors M1 and M2 control the charge current and INTERNAL TRICKLE CHARGE CURRENT SOURCE provide voltage regulation. The latter is used as the top off An internal current source between BP and BATTISNS change voltage, and as the regulated supply voltage to the provides small currents to the battery, in case of trickle application, in case of dead battery operation. In order to charging a dead battery. support dead battery operation, a so called "serial path" charging configuration including M3 needs to be used. Then COMPARATORS in case of a dead battery, the transistor M3 is made nonThe charger detection is based on three comparators. The conducting and the internal trickle charge current charges the "charger valid", which monitors CHRGRAW, the "charger battery. If the battery is sufficiently charged, the transistor M3 presence", which monitors the voltage drop between is made conducting which connects the battery to the CHRGRAW and BPSNS, and the "CHGCURR" comparator, application, just like during normal operation without a which monitors the current through the sense resistor charger. In so called single path charging, M3 is replaced by connected between CHRGISNS and BPSNS. A charger a short and the pin BATTFET must be floating. Dead battery insertion is detected, based on the charger presence operation is not supported in that case. Transistors M1 and comparator and the "charger valid" comparator both going M2 become non-conducting if the charger voltage is too high. high. For all but the lowest current setting, a charger removal The UVBUS pin must be shorted to CHRGRAW in cases is detected, based on both the "charger presence" where the charger is being supplied from the USB cable. A comparator going low and the charger current falling below current can be supplied from the battery to an accessory with CHGCURR. In addition, for the lowest current settings, or if all transistors M1, M2, and M3 conducting by enabling the not charging, the "charger valid" comparator going low is an reverse supply mode. An unregulated wall charger additional cause for charger removal detection. configuration can be built, in which case CHRGSE1B must be In addition to the aforementioned comparators, three more pulled low. The battery current monitoring resistor R1 and the comparators play a role in battery charging. These charge LED indicator are optional. comparators are "BATTMIN", which monitors BATT for the safe charging battery voltage, "BATTON", which monitors CHARGE PATH REGULATOR BATT for the safe operating battery voltage, and M1 and M2 are permanently used as a combined pass "BATTCYCL", which monitors BPSNS for the constant device for a super regulator, with a programmable output current to constant voltage transition. The BATTMIN and voltage and programmable current limit. BATTON comparators have a normal and a long (slow) The voltage loop consists of M1, M2, and an amplifier with debounced output. The slow output is used in some places in voltage feedback taken from the BPSNS pin. The value of the the charger flow to provide enough time to the battery sense resistor is of no influence on the output voltage. The protection circuit to reconnect the battery cell. output voltage is programmable by SPI from 3.8 to 4.45 V. The current loop is composed of the M1 and M2 as control BATTERY THERMISTOR CHECK CIRCUITRY elements, the external sense resistor, a programmable A battery pack may be equipped with a thermistor, which current limit, and an amplifier. The control loop will regulate value decreases over temperature. the voltage drop over the external resistor. The charge By default, the battery thermistor value is taken into current is programmable by SPI from 0 to 1600 mA. account for charging the battery
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION
CHARGE LED INDICATOR
Since normal LED control via the SPI bus is not always possible in the standalone operation, a current sink is provided at the CHRGLED pin. The driver at CHRGLED serves as the trickle (sign of life) LED and will be activated when standalone charging is started, and will remain on also when the device is powered on, until the charger is programmed by SPI.
PROTECTION FUNCTIONS
OVER-VOLTAGE PROTECTION
In order to protect the application, the voltage at the CHRGRAW pin is monitored. When crossing the threshold (16 V high to low and low to high), the charge path regulator will be turned off by opening the mosfets connected to pins CHRGCTRL1 and CHRGCTRL2. An interrupt CHGFAULTI is generated with the associated CHGFAULTM mask bit. In order to ensure immediate protection, the control of M1, M2, and M3 occurs in real time. The UVBUS pin is also protected against over-voltages. This will occur at much lower levels then for CHRGRAW. When a VBUS over-voltage is detected the internal circuitry of the USB block is disconnected. An USBOVI is generated in this case. When the maximum voltage of the IC is exceeded, damage will occur to the IC, and the state of the mosfets connected to pins CHRGCTRL1 and CHRGCTRL2 cannot be guaranteed. If one wants to protect against these failure conditions, additional protection will be required. The same is valid for charger polarity inversion protection.
MODES OF OPERATION
REVERSE SUPPLY MODE
The battery voltage can be applied to an external accessory via the charge path. The path is only established if the normal charge path is disabled. The turn on of M1 and M2 is intentionally slow. The current through the accessory supply path is monitored via the charge path sense resistor R2. It can be read out via the ADC. The accessory supply path is disabled and an interrupt CHGSHORTI is generated when the slow threshold or the fast threshold is crossed. The reverse path is disabled when a current reversal occurs, and an interrupt CHREVI is generated. This function operates up to 40C.
OVER-POWER DISSIPATION PROTECTION STANDALONE CHARGING
A standalone charge mode of operation is provided to minimize software interaction. It also allows that a completely discharged battery can be revived without processor control. This is especially important when charging from a USB host or when the optional transistor M3 is not placed. Since the charge path operates in a linear fashion, the dissipation can be significant and care must be taken to ensure that the external pass FETs M1 and M2 are not over dissipating when charging. By default, the charge system will protect against this by a built in power limitation circuit.This circuit will monitor the voltage drop between CHRGRAW and CHRGISNS, and the current through the external sense resistor connected between CHRGISNS and BPSNS. When required, a duty cycle is applied to the FETs connected on CHRGCTRL1 and CHRGCTRL2, and thus the charge current, in order to stay within the power budget. At the same time the FET connected to BATTFET pin is forced to conduct to keep the application powered. In case of excessive supply conditions, the power limiter minimum duty cycle may not be sufficiently small to maintain the actual power dissipation within budget. In that case, the charge path will be disabled and the CHGFAULTI interrupt generated. The power budget can be programmed by the SPI through the PLIM[1:0] bits, which establishes a power limit from 600 to 1200 mW in 200 mV steps. The power dissipation limiter can be disabled by setting the PLIMDIS bit. In this case, it is advised to use close software control to estimate the dissipated power in the external pass FETs. The power limiter is automatically disabled in serial path factory mode and in reverse mode. Since a charger attachment can be a Turn On event when a product is initially in the Off state, any nondefault settings that are intended for PLIM[1:0] and PLIMDIS should be programmed early in the configuration sequence to ensure proper supply conditions adapted to the application. To avoid any false detection during power up, the power limiter output is blanked at the start of the charge cycle. As a safety
SOFTWARE CONTROLLED CHARGING
The charger can also be operated under software control. In this mode, full control of the charger settings is assumed by software; the state machine will no longer determine the mode of charging.
FACTORY MODE
In factory mode, power is provided to the application with no battery present. It is not a situation which should occur in the field. The factory mode is differentiated from a USB Host by, in addition to a valid VBUS, a UID being pulled high to VBUS level during the attach, See Connectivity (USB Interface) on page 63.
USB LOW POWER BOOT
USB low power boot allows the application to boot with a dead battery within the 100 mA USB budget, until the processor has negotiated for the full current capability. This mode expedites the charging of the dead battery and allows the software to bring up the LCD display screen with the message "Charging battery".
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precaution, the power dissipation is monitored and the desired duty cycle is estimated. When this estimated duty cycle falls below the power limiter minimum duty cycle, the charger circuit will be disabled.
Channel 5 ADIN5, Battery Thermistor and Battery Detect: On channel 5, ADIN5 may be used as a general purpose input, but in a typical application, ADIN5 is used to read out the battery pack thermistor. The thermistor will have to be biased with an external pull-up to a voltage rail greater than the ADC input range. In order to save current when the thermistor reading is not required, it can be biased from one of the general purpose IOs such as GPO1. A resistor divider network should assure the resulting voltage falls within the ADC input range, especially when the thermistor check function is used. When the application is on and supplied by the charger, a battery removal can be detected by a battery thermistor presence check. When the thermistor terminal becomes high-impedance, the battery is considered being removed. This detection function is available at the ADIN5 input. Channel 6 ADIN6 and Coin Cell Voltage: On channel 6, ADIN6 may be used as a general purpose unscaled input but in a typical application, the PA thermistor is connected here. In addition, on channel 6, the voltage of the coin cell connected to the LICELL pin can be read. Channel 7 ADIN7 and ADIN7B, UID and Die Temperature: On channel 7, ADIN7 may be used as a general purpose input. In a typical application, an ambient light sensor is connected here. A second general purpose input ADIN7B is available. In the application, a second ambient light sensor is supposed to be connected here. In addition, on channel 7, the voltage of the USB ID line connected to the UID pin and the die temperature can be read.
ADC SUBSYSTEM
The ADC core is a 10 bit converter. The ADC core and logic run on 2/3 of the switcher PLL generated frequency, so approximately 2.0 MHz. If an ADC conversion is requested while the PLL is not active, it will be automatically enabled by the ADC. A 32.768 kHz equivalent time base is derived from the 2.0 MHz clock to time ADC events. The ADC is supplied from VCORE. The ADC core has an integrated auto calibration circuit which reduces the offset and gain errors. The switcher PLL is programmable, so when the switcher frequency is changed, the frequency applied to the ADC converter will change accordingly. Although the conversion time is inversely proportional to the PLLX[2:0] setting, this will not influence the ADC performance. The locally derived 32.768 kHz will remain constant in order to not influence the different timings depending on this time base. The ADC Subsystem has 8 channels: Channel 0 Battery Voltage: The battery voltage is read at the BATT pin at channel 0. Channel 1 Battery Current: The current flowing out of and into the battery can be read via the ADC by monitoring the voltage drop over the sense resistor between BATT and BATTISNSCC. Channel 2 Application Supply: The application supply voltage is read at the BP pin at channel 2. Channel 3 Charger Voltage: The charger voltage is measured at the CHRGRAW pin at channel 3. Channel 4 Charger Current: The charge current is read by monitoring the voltage drop over the charge current sense resistor. This resistor is connected between CHRGISNS and BPSNS.
COULOMB COUNTER
As discussed previously, the current into and from the battery can be read out through the general purpose ADC as a voltage drop over the R1 sense resistor. Together with the battery voltage reading the battery capacity can be estimated. A more accurate battery capacity estimation can be obtained by using the integrated Coulomb Counter. The Coulomb Counter (or CC) monitors the current flowing in/out of the battery by integrating the voltage drop across the battery current sense resistor R1, followed by an A to D conversion. The result of the A to D conversion is used to increase/decrease the contents of a counter that can be read out by software.
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Figure 12. 13892 Coulomb Counter Block Diagram.
PROTECTIONS AGAINST FAULT CONDITIONS Counter roll over: CCOUT[15:0]=8000HEX
This occurs when the contents of CCOUT[15:0] go from a negative to a positive value or vice versa. Software may interpret incorrectly the battery charge by this change in polarity. When CCOUT[15:0] becomes equal to 8000HEX the CCFAULT is set. The counter stays counting so its contents can still be exploited. Battery removal: `BP13892
screen X plate is connected to TSX1 and TSX2, while the Y plate is connected to TSY1 and TSY2. A local supply TSREF will serve as a reference. Several readout possibilities are offered. To perform touch screen readings, the processor will have to select the touch screen mode, program the delay between the conversions via the ATO and ATOX settings, trigger the ADC via one of the trigger sources, wait for an interrupt indicating the conversion is done, and then read out the data. In order to reduce the interrupt rate and to allow for easier noise rejection, the touch screen readings are repeated in the readout sequence. The reference for the touch screen is
TSREF and is powered from VCORE. In touch screen operation, TSREF is a dedicated regulator that is to say, no other loads than the touch screen should be connected here.
Table 17. 13892 Touch Screen ADC Readings
ADC CONVERSION 0 1 2 3 4 5 6 7 SIGNALS SAMPLED X position X position Dummy Y position Y position Dummy Contact resistance Contact resistance
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The dummy conversion inserted between the different readings is to allow the references in the system to be prebiased for the change in touch screen plate polarity and will read out as `0'.
MODES OF OPERATION
In inactive mode, the inputs TSX1, TSX2, TSY1, and TSY2 can be used as general purpose inputs. They are respectively mapped on ADC channels 4, 5, 6, and 7. In interrupt mode, a voltage is applied to the X-plate (TSX2) via a weak current source to VCORE, while the Yplate is connected to ground (TSY1). When the two plates make contact both will be at a low potential. This will generate a pen interrupt TSI to the processor. This detection does not make use of the ADC core or the TSREF regulator, so both can remain disabled. In touch screen mode, the XY coordinate pairs and the contact resistance are read. The X-coordinate is determined by applying TSREF over the TSX1 and TSX2 pins while performing a high-impedance reading on the Y-plate through TSY1. The Y-coordinate is determined by applying TSREF between TSY1 and TSY2 while reading the TSX1 pin. The contact resistance is measured by applying a known current into the TSY1 terminal of the touch screen and through the terminal TSX2, which is grounded. The voltage difference between the two remaining terminals TSY2 and TSX1 is measured by the ADC, and equals the voltage across the contact resistance. Measuring the contact resistance helps in determining if the touch screen is touched with a finger or stylus.
42 mA respectively. This facilitates the current setting, in case two or more serial LED strings are connected in parallel to the same driver, or when using super bright LEDs. The boost switcher SWLED supplying the backlight LEDs is shared between all three backlight drivers. However, a maximum of only two backlight drivers can be activated at the same time, for instance the main display plus keypad. If all three backlight drivers are enabled meaning none of the duty cycles equals 0/32, then none of the drivers will be activated.
SIGNALING LED DRIVERS
The signaling LED drivers LEDR, LEDG, and LEDB are independent current sink channels. Each driver channel features programmable current levels from 0 to 21 mA as well as programmable PWM duty cycle settings. By a combination of level and PWM settings, each channel provides flexible LED intensity control. By driving LEDs of different colors, color mixing can be achieved. Blue LEDs or bright green LEDs require more headroom than red and normal green signal LEDs. In the application, a 5.0 V or equivalent supply rail is therefore required. This is provided by the integrated boost converter SWBST. As with the backlight driver channels, the signaling LED drivers include ramp up and ramp down patterns are implemented in hardware. In addition, programmable blink rates are provided. Blinking is obtained by lowering the PWM repetition rate of each of the drivers, while the on period is determined by the duty cycle setting. To avoid high frequency spur coupling in the application, the switching edges of the output drivers are softened."
LED DRIVERS FOR LIGHTING SYSTEM
BACKLIGHT LED DRIVERS
The lighting system includes backlight drivers for main display, auxiliary display, and keypad. The backlight LEDs are configured in series and supplied from an inductive boost supply See Boost Converters on page 53. Three additional drivers are provided for RGB or general purpose signaling. Ramp up and ramp down patterns are implemented in hardware to reduce the burden of real time software control via the SPI, to orchestrate dimming and soft start lighting effects. These patterns are guaranteed by design. The current level is programmable in a low range mode and in a high range mode from 0 to 21 mA and from 0 to
CONNECTIVITY (USB INTERFACE)
The 13892 contains the regulators required to supply the PHY contained in the i.MX51, i.MX37, i.MX35, and i.MX27 processors. The regulators used to power the external PHY in the i.MX51 and i.MX37 are VUSB, VUSB2, and VUSB for the i.MX35 and i.MX27 processors. The IC also provides the 5.0 V supply for USB OTG operation. The USB interface may be used for portable product battery charging. Finally included are comparators/detectors for VBUS and ID detection. VBUS is the power rail of the USB cable that must be connected to the UVBUS pin. The USB interface is illustrated in Figure 13.
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Figure 13. 13892 USB Interface Block Diagram
OTG MODE (ON THE GO)
The ID detector is primarily used to determine if a mini-A or mini-B style plug has been inserted into a mini-AB style receptacle on the application. However, it also supports two additional modes which are outside of the USB standards: a factory mode, and a non-USB accessory mode. The state of the ID detection can be read via the SPI to poll dedicated sense bits for a floating, grounded, or factory mode condition on the UID pin. There are also dedicated maskable interrupts for each UID condition as well. Since portable applications have limited capabilities, this supplement to the USB2.0 specification was developed in order to allow a portable device to take the role of a USB host. In this mode of operation, SWBST is internally switched to
Parameter VBUS input impedance UID 220K Pull-up(57) UID Pull-up
(57)
supply the VUSB regulator, and SWBST will drive VBUS from the VUSBIN pin as long as VBUSEN pin is a logic high = 1. According to the USB2.0 specification, the USB host is the device where the USB Host Controller is installed, through which it interacts with the USB devices. The USB host is responsible for: * Detecting the attachment and removal of USB devices. * Managing control flow between the host and USB devices. * Managing data flow between the host and USB devices. * Collecting status and activity statistics. * Providing power to attached USB devices. When working in host mode, VUSB is supplied from the VBUS wire of the USB cable (VBUS).
Condition Min 40 132 4.75 60 220 5 100 Typ Max 100 308 5.25 140 Units K K uA K
As A_device IDPUCNTRL=0, Resistor to VCORE IDPUCNTRL=1, Current source from VCORE ID100KPU=1, Resistor to VCORE
UID Parallel Pull-up(57)
Notes 57. Note that the UID Pull-ups are not mutually exclusive of each other, they are independently controlled by their enable bits and thus multiple pull-ups can be engaged simultaneously.
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POWER CONTROL LOGIC (STATE MACHINE)
The power control system interfaces with the processor via different IO signals and the SPI bus. It also uses on chip signals and detector outputs.
Figure 14 shows the flow of the power control state machine. This diagram serves as the basis for the description of Operational Modes.
Figure 14. Power Control Logic (State Machine)
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OPERATIONAL MODES
The following are text descriptions of the power states of the system with additional details of the state machine to complement Figure 14. Note that SPI control is only possible in the Watchdog, On, and User Off Wait states, and that the interrupt line INT is kept low in all states except for Watchdog and On. in response to an intentional Turn Off by the end user. The only exit then will be a Turn On event. To an end user, the Memory Hold and User Off states look like the product has been shut down completely. However, a faster startup is facilitated by maintaining external memory in self-refresh mode (Memory Hold and User Off mode), as well as powering portions of the processor core for state retention (User Off only).
OFF
If the supply at BP is above the UVDET threshold, only the IC core circuitry at VCOREDIG and the RTC module are powered. All other supplies are inactive. To exit the Off mode, a valid turn on event is required. No specific timer is running in this mode. If the supply at BP is below the UVDET threshold, no turn on events are accepted. If a valid coincell is present, the core gets its power from LICELL. The only active circuitry is the RTC module, and the BP greater than UVDET detection.
MEMORY HOLD
RESETB and RESETBMCU are low, and both CLK32K and CLK32KMCU are disabled (CLK32KMCU active if DRM is set). Upon a Turn On event, the Cold Start state is entered, the default power up values are loaded, and the MEMHLDI interrupt bit is set. A Cold Start out of the Memory Hold state will result in shorter boot times compared to starting out of the Off state, since software does not have to be loaded and expanded from flash. The startup out of Memory Hold is also referred to as Warm Boot. No specific timer is running in this mode.
COLD START
This is entered upon a Turn On event from Off, Warm Boot, successful PCUT, or Silent System Restart. The first 8.0 ms are used for initialization which includes bias generation, PUMS / configuration latching, and qualification of the input supply level BP. The switchers and regulators are then powered up sequentially to limit the inrush current. The reset signals RESETB and RESETBMCU are kept low. The Reset timer starts running when entering Cold Start. The input control pins WDI and STANDBYx are ignored.
USER OFF
RESETB is low and RESETBMCU is kept high. The 32 kHz peripheral clock driver CLK32K is disabled; CLK32KMCU (connected to the processor's CKIL input) is maintained in this mode, if the CLK32KMCUEN and USEROFFCLK bits are both set, or if DRM is set. Any peripheral loading on SW1 and/or SW2 should be isolated from the output node(s) by the PWGT1 switch, which opens in both low power Off modes, due to the RESETB transition. In this way, leakage is minimized from the power domain, maintaining the processor core. Since power is maintained for the core (which is put into its lowest power state), and since MCU RESETBMCU does not trip, the processor's state may be quickly recovered when exiting USEROFF upon a Turn On event. The CLK32KMCU clock can be used for very low frequency / low power idling of the core(s), minimizing battery drain while allowing a rapid recovery from where the system left off before the USEROFF command. Upon a Turn On event, Warm Start state is entered, and the default power up values are loaded. A Warm Start out of User Off will result in an almost instantaneous startup of the system, since the internal states of the processor were preserved along with external memory. No specific timer is running in this mode.
WATCHDOG
The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The Watchdog timer starts running when entering the Watchdog state. When expired, the system transitions to the On state, where WDI will be checked and monitored. The input control pins WDI and STANDBYx are ignored while in the Watchdog state.
ON
The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The WDI pin must be high to stay in this mode.
USER OFF WAIT
The system is fully powered and under SPI control. The WDI pin no longer has control over the part. The Wait mode is entered by a processor request for User Off. The Wait timer starts running when entering User Off Wait mode. This leaves the processor time to suspend or terminate its tasks.
WARM START
Entered with a Turn On event from User Off. The first 8.0 ms is used for initialization which includes bias generation, PUMS latching, and qualification of the input
MEMORY HOLD AND USER OFF (LOW POWER OFF STATES)
As noted in the User Off Wait description, the system is directed into low power Off states, based on a SPI command
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supply level BP. The switches and regulators are then powered up sequentially to limit the inrush current. RESETB is kept low and RESETBMCU is kept high. CLK32KMCU is kept active if CLK32KMCU was set. The reset timer starts running when entering Warm Start. When expired, the Warm Start state is exited for the Watchdog state, a WARMI interrupt is generated, and RESETB will go high.
INTERNAL MEMHOLD POWER CUT
Power Cut description: When the supply at BP drops below the UVDET threshold due to battery bounce or battery removal, the Internal MemHold Power Cut mode is entered and a Power Cut (PCUT) timer starts running. The backup coin cell will now supply the RTC as well as the on chip memory registers and some other power control related bits. All other supplies will be disabled. Internal MemHold Power Cut: As previously described, a momentary power interruption will put the system into the Internal MemHold Power Cut state if PCUTs are enabled. The backup coin cell will now supply 13892's core along with the 32 k crystal oscillator, the RTC system and coin cell backed up registers. All regulators and switchers will be shut down to preserve the coin cell and RTC as long as possible. Both RESETB and RESETBMCU are tripped, bringing the entire system down along with the supplies and external clock drivers, so the only recovery out of a Power Cut state is to reestablish power and initiate a Cold Start.
current. Therefore, no specific control is required to put these regulators in a low power mode (i.e., "On" implies an adaptive mode control" based on load current). Bits are reserved in case the automatic scheme shows to be insufficient. The regulators with external pass devices (VSD, VVIDEO, VGEN1, and VGEN2) can also operate in a normal and low power mode. However, since a load current detection cannot be performed for these regulators, the transition between both modes is not automatic, and is controlled by setting the corresponding mode bits for the operational behavior desired. The regulators VGEN3, and VCAM can be configured for using the internal pass device or external pass device as explained in LDOs on page 54. Therefore, depending on the configuration selected, the automatic low power mode is or is not available.
BUCK SWITCHERS
Operational modes of the Buck switchers can be controlled by direct SPI programming, altered by the state of the STANDBY pins, by direct state machine influence (i.e., entering Off or low power Off states, for example), or by load current magnitude when so configured. Available modes include PWM with No Pulse Skipping (PWM), PWM with Pulse Skipping (PWMPS), Pulse Frequency Mode (PFM), and Off. The transition between the two modes PWMPS and PFM can occur automatically based on the load current (auto). Therefore, no specific control is required to put the switchers in a low power mode. When the buck switchers are not configured in the auto mode, power savings may be achieved by disabling the switchers when not needed, or running them in PFM mode, if loading conditions are light enough. SW1, SW2, SW3, and SW4 can be configured for mode switching with STANDBY or autonomously, based on load current with adaptive mode control (Auto). Additionally, provisions are made for maintaining PFM operation in USEROFF and MEMHOLD modes, to support state retention for faster startup from the low power Off modes, for Warm Start or Warm Boot.
POWER SAVING
SYSTEM STANDBY
A product may be designed to go into DSM after periods of inactivity, such as if a music player completes a play list and no further activity is detected, or if a gaming interface sits idle for an extended period. Two Standby pins are provided for board level control of timing in and out of such deep sleep modes. When a product is in DSM it may be able to reduce the overall platform current by lowering the switcher output voltage, disabling some regulators, or forcing GPOx low. This can be obtained by SPI configuration of the Standby response of the circuits along with control of the Standby pins. To ensure that shared resources are properly powered when required, the system will only be allowed into Standby when both the application processor (which typically controls the STANDBY pin) and peripherals (which typically control the STANDBYSEC pin) allow it--this is referred to as a Standby event.
POWER GATING SYSTEM
The low power Off states are provided to allow faster system booting from two pseudo Off conditions: Memory Hold, which keeps external memory powered for self refresh, and User Off, which keeps the processor powered up for state retention. For reduced current drain in low power Off states, parts of the system can benefit from power gating, to isolate the minimum essentials for such operational modes. It is also necessary to ensure that the power budget on backed up domains is within the capabilities of switchers in PFM mode. An additional benefit of power gating peripheral loads during system startup is to enable the processor core to complete booting and begin running software before additional supplies or peripheral devices are powered. This allows system software to bring up the additional supplies and close power gating switches in the most optimum order
REGULATOR MODE CONTROL
The regulators with embedded pass devices (VDIG, VPLL, VIOHI, VUSB, VUSB2, and VAUDIO) operate in two modes: a normal mode, and a low power mode. The transition between both modes occurs automatically, based on the load
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to avoid problems with supply sequencing or transient current surges. The power gating switch drivers and integrated control are included for optimizing the system power tree. The power gate drivers could be used for other general power gating as well. The text herein assumes the standard application of PWGT1 for core supply power gating and PWGT2 for Memory Hold power gating.
USER OFF POWER GATING
User Off configuration maintains PFM mode switchers on both the processor and external memory power domains. PWGTDRV1 is provided for power gating peripheral loads sharing the processor core supply domain(s) SW1, and/or SW2, and/or SW3. In addition, PWGTDRV2 provides support to power gate peripheral loads on the SW4 supply domain. In a typical application, SW1, SW2, and SW3 will be kept active for the processor modules in state retention, and SW4 will be retained for the external memory in self refresh mode. SW1, SW2, and SW3 power gating FETs drive would typically be connected to PWGTDRV1 (for parallel NMOS switches). The SW4 power gating FET drive would typically be connected to PWGTDRV2. When low power Off mode is activated, the power gate drive circuitry will be disabled, turning off the NMOS power gate switches, to isolate the maintained supply domains from any peripheral loading.
Memory Hold, so just the external memory is maintained in self-refresh mode. An external NMOS is to be placed between the directconnected memory supply and any peripheral loading. The PWGTDRV2 pin controls the gate of the external NMOS, and is normally pulled up to a charge pumped voltage (~5.0 V). During Memory Hold or User Off, PWGTDRV2 will go low to turn off the NMOS switch and isolate memory on the SW4 power domain.
POWER DISSIPATION
During operation, the temperature of the die should not exceed the maximum junction temperature. Depending on the operating ambient temperature and the total internal dissipation, this limit can be exceeded. To optimize the thermal management scheme and avoid overheating, the 13892 provides a thermal management system. The thermal protection is based on a circuit with a voltage output that is proportional to the absolute temperature. This voltage can be read out via the ADC for precise temperature readouts (See Functional Device Operation).
THERMAL PROTECTION
Thermal protection is integrated to power off the 13892 and disable the charger circuitry in case of over dissipation. This thermal protection will act above the maximum junction temperature to avoid any unwanted power downs. The protection is debounced by one period of the 32kHz clock in order to suppress any (thermal) noise. This protection should be considered as a fail-safe mechanism and therefore the application design should be dimensioned such that this protection is not tripped under normal conditions. The temperature thresholds are listed in the last section of Table 4.
MEMORY HOLD POWER GATING
As with the User Off power gating strategy described previously, Memory Hold power gating is intended to allow isolation of the SW4 power domain to selected circuitry in low power modes, while cutting off the switcher domain from other peripheral loads. The only difference is that processor supplies SW1, and/or SW2, and/or SW3 are shut down in
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TYPICAL APPLICATIONS
Figure 15. 13892 Typical Application
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PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
VK SUFFIX 139-PIN 98ASA10820D REVISION 0
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VK SUFFIX 139-PIN 98ASA10820D REVISION 0
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REVISION HISTORY
REVISION 1.0 2.0 DATE 10/2009 10/2009 DESCRIPTION OF CHANGES * * Initial release Updated Status to Advance Information.
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Analog Integrated Circuit Device Data Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages.
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FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2009. All rights reserved. MC13892 Rev. 2.0 10/2009

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